ADC-DSP-Based 10-to-112-Gb/s Multi-Standard Receiver in 7-nm FinFET von Lin, Haidang, Boecker, Charlie, Hossain, Masum, Tangirala, Shankar, Vu, Roxanne, Vamvakos, Socrates D., Groen, Eric, Li, Simon, Choudhary, Prashant, Wang, Nanyan, Shibata, Masumi, Taghavi, Hossein, van Ierssel, Marcus, Maniyar, AdilHussain, Wodkowski, Adam, Brar, Kulwant, Nguyen, Nhat, Desai, Shaishav

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10-to-112-Gb/s DSP-DAC-Based Transmitter in 7-nm FinFET With Flex Clocking Architecture von Groen, Eric, Boecker, Charlie, Hossain, Masum, Vu, Roxanne, Vamvakos, Socrates D., Lin, Haidang, Li, Simon, Van Ierssel, Marcus, Choudhary, Prashant, Wang, Nanyan, Shibata, Masumi, Taghavi, Mohammad Hossein, Brar, Kulwant, Nguyen, Nhat, Desai, Shaishav

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Spurious-Free Time-to-Digital Conversion in an ADPLL Using Short Dithering Sequences von Waheed, K., Staszewski, R. B., Dulger, F., Ullah, M. S., Vamvakos, S. D.

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An Intelligent RAM with Serial I/Os von Kleveland, Bendik, Miller, Michael John, David, Ronald B., Patel, Jay, Chopra, Rajesh, Sikdar, Dipak K., Kumala, Jeff, Vamvakos, Socrates D., Morrison, Mike, Liu, Ming, Balachandran, Jayaprakash

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Discrete-Time, Linear Periodically Time-Variant Phase-Locked Loop Model for Jitter Analysis von Vamvakos, S D, Stojanovic, V, Nikolic, B

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A 2.488–11.2 Gb/s SerDes in 40 nm low-leakage CMOS with multi-protocol compatibility for FPGA applications von Vamvakos, Socrates D., Gauthier, Claude R., Rao, Chethan, Wang, Alvin, Canagasaby, Karthisha Ramoshan, Abugharbieh, Khaldoon, Choudhary, Prashant, Dabral, Sanjay, Desai, Shaishav, Hassan, Mahmudul, Hsieh, K. C., Kleveland, Bendik, Mandal, Gurupada, Rouse, Richard, Saraf, Ritesh, Yeung, Jason, Cao, Ying

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A 2.488a11.2 Gb/s SerDes in 40 nm low-leakage CMOS with multi-protocol compatibility for FPGA applications von Vamvakos, Socrates, Gauthier, Claude, Rao, Chethan, Wang, Alvin, Canagasaby, Karthisha, Abugharbieh, Khaldoon, Choudhary, Prashant, Dabral, Sanjay, Desai, Shaishav, Hassan, Mahmudul, Hsieh, K, Kleveland, Bendik, Mandal, Gurupada, Rouse, Richard, Saraf, Ritesh, Yeung, Jason, Cao, Ying

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Computationally efficient, event-driven simulation of wireless transmitters using a noisy local oscillator von Vamvakos, Socrates D, Jingcheng Zhuang, Waheed, Khurram

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Noise Analysis of Time-to-Digital Converter in All-Digital PLLs von Vamvakos, S.D., Bogdan Staszewski, R., Sheba, M., Waheed, K.

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Spurious free time-to-digital conversion in an ADPLL using short dithering sequences von Waheed, K, Sheba, M, Staszewski, R B, Dulger, F, Vamvakos, S D

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A 2.488-11.2 Gb/s multi-protocol SerDes in 40nm low-leakage CMOS for FPGA applications von Vamvakos, S. D., Gauthier, C. R., Rao, Chethan, Canagasaby, K. R., Choudhary, P., Dabral, S., Desai, S., Hassan, M., Hsieh, K. C., Kleveland, B., Mandal, G., Rouse, R., Saraf, R., Wang, A., Yeung, J., Abugharbieh, K., Ying Cao

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Discrete-time, cyclostationary phase-locked loop model for jitter analysis von Vamvakos, S.D., Stojanovic, V., Nikolic, B.

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DIGITAL PHASE LOCKED LOOP WITH DITHERING von SHEBA MAHBUBA, WAHEED KHURRAM, STASZEWSKI ROBERT BOGDAN, VAMVAKOS SOCRATES

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Digital phase locked loop with dithering von Waheed, Khurram, Sheba, Mahbuba, Staszewski, Robert Bogdan, Vamvakos, Socrates

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Digital phase locked loop with dithering von SHEBA MAHBUBA, WAHEED KHURRAM, STASZEWSKI ROBERT BOGDAN, VAMVAKOS SOCRATES

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DIGITAL PHASE LOCKED LOOP WITH DITHERING von SHEBA MAHBUBA, WAHEED KHURRAM, STASZEWSKI ROBERT BOGDAN, VAMVAKOS SOCRATES

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Digital phase locked loop with dithering von SHEBA MAHBUBA, WAHEED KHURRAM, STASZEWSKI ROBERT BOGDAN, VAMVAKOS SOCRATES

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Digital phase locked loop with dithering von Waheed, Khurram, Sheba, Mahbuba, Staszewski, Robert Bogdan, Vamvakos, Socrates

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DIGITAL PHASE LOCKED LOOP WITH DITHERING von SHEBA MAHBUBA, WAHEED KHURRAM, STASZEWSKI ROBERT BOGDAN, VAMVAKOS SOCRATES

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PLL On-Chip Jitter Measurement: Analysis and Design von Vamvakos, S.D., Stojanovic, V., Zerbe, J.L., Werner, C.W., Draper, D., Nikolic, B.

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