Evaluating register allocation and instruction scheduling techniques in out-of-order issue processors von Valluri, M.G., Govindarajan, R.

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Two-level representative workload phase detection von VALLURI MADHAVI GOPAL, BELL, JR. ROBERT H, INDUKURU VENKAT RAJEEV, SESHADRI PATTABI MICHAEL, CHEN WEN-TZER THOMAS

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Two-level representative workload phase detection von Bell, Jr, Robert H, Chen, Wen-Tzer Thomas, Indukuru, Venkat Rajeev, Seshadri, Pattabi Michael, Valluri, Madhavi Gopal

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Evaluating Register Allocation and Instruction Scheduling Techniques in Out-Of-Order Issue Processors von Valluri, Madhavi Gopal, Govindarajan, R.

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Method and apparatus for integrated circuit design model performance evaluation using basic block vector clustering and fly-by vector clustering von Bell, Jr, Robert H, Chen, Wen-Tzer Thomas, Indukuru, Venkat Rajeev, Seshadri, Pattabi Michael, Valluri, Madhavi Gopal

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Method and apparatus for integrated circuit design model performance evaluation using basic block vector clustering and fly-by vector clustering von VALLURI MADHAVI GOPAL, BELL, JR. ROBERT H, INDUKURU VENKAT RAJEEV, SESHADRI PATTABI MICHAEL, CHEN WEN-TZER THOMAS

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TWO-LEVEL REPRESENTATIVE WORKLOAD PHASE DETECTION METHOD, APPARATUS, AND COMPUTER USABLE PROGRAM CODE von VALLURI MADHAVI GOPAL, BELL, JR. ROBERT H, INDUKURU VENKAT RAJEEV, SESHADRI PATTABI MICHAEL, CHEN WEN-TZER THOMAS

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Evidence-based National Vaccine Policy von Madhavi, Y, Puliyel, Jacob M, Mathew, Joseph L, Raghuram, N, Phadke, Anant, Shiva, Mira, Srinivasan, S, Paul, Yash, Srivastava, R N, Parthasarathy, A, Gupta, Sunil, Ranga, Udaykumar, Lakshmi, V Vijaya, Joshi, Nayana, Nath, Indira, Gulhati, C M, Chatterjee, Prabir, Jain, Anuradha, Priya, Ritu, Dasgupta, Rajib, Sridhar, S, Dabade, Gopal, Gopakumar, K M, Abrol, Dinesh, Santhosh, M R, Srivastava, Sadhana, Visalakshi, S, Bhargava, Anurag, Sarojini, N B, Sehgal, Devinder, Selvaraj, Sakthivel, Banerji, D

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Dental age estimation methods applied to Indian children and adolescents: A systematic review and meta-analysis von Shoukath, A., Vidigal, M.T.C., Vieira, W., Paranhos, L.R., Mânica, S., Franco, A.

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Panel of Reviewers

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Method and apparatus for modulo scheduled loop execution in a processor architecture von Hwu, Wen-mei W, Merten, Matthew C

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