An Asynchronous Power Aware and Adaptive NoC Based Circuit von Beigne, E., Clermidy, F., Lhermet, H., Miermont, S., Thonnart, Y., Xuan-Tu Tran, Valentian, A., Varreau, D., Vivet, P., Popon, X., Lebreton, H.

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Automatic Gate Biasing of an SCCMOS Power Switch Achieving Maximum Leakage Reduction and Lowering Leakage Current Variability von Valentian, A., Beigne, E.

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3D monolithic integration: Technological challenges and electrical results von Vinet, M., Batude, P., Tabone, C., Previtali, B., LeRoyer, C., Pouydebasque, A., Clavelier, L., Valentian, A., Thomas, O., Michaud, S., Sanchez, L., Baud, L., Roman, A., Carron, V., Nemouchi, F., Mazzocchi, V., Grampeix, H., Amara, A., Deleonibus, S., Faynot, O.

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Power Reduction of Asynchronous Logic Circuits Using Activity Detection von Thonnart, Y., Beigne, E., Valentian, A., Vivet, P.

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A single TSV-rail 3D quasi delay insensitive asynchronous signaling von Belleville, M, Beigne, E, Valentian, A

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Modeling subthreshold SOI logic for static timing analysis von Valentian, A., Thomas, O., Vladimirescu, A., Amara, A.

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Power switch optimization and sizing in 65nm PD-SOI considering supply voltage noise von Le Coz, J, Valentian, A, Flatresse, P, Belleville, M

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65nm PD-SOI glitch-free Retention Flip-Flop for MTCMOS power switch applications von Le-Coz, J, Flatresse, P, Clerc, S, Belleville, M, Valentian, A

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Design and Cryogenic Operation of a Hybrid Quantum-CMOS Circuit von Clapera, P., Ray, S., Jehl, X., Sanquer, M., Valentian, A., Barraud, S.

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SOI partially-depleted ultra low voltage memory and digital circuit design von Thomas, O., Amara, A., Valentian, A.

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Compact 6T SRAM cell with robust read/write stabilizing design in 45nm Monolithic 3D IC technology von Thomas, O., Vinet, M., Rozeau, O., Batude, P., Valentian, A.

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Design challenges for nano-scale devices von Belleville, M., Thomas, O., Valentian, A., Clermidy, F.

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Investigation on TSV impact on 65nm CMOS devices and circuits von Chaabouni, H, Rousseau, M, Leduc, P, Farcy, A, El Farhane, R, Thuaire, A, Haury, G, Valentian, A, Billiot, G, Assous, M, De Crecy, F, Cluzel, J, Toffoli, A, Bouchu, D, Cadix, L, Lacrevaz, T, Ancey, P, Sillon, N, Flechet, B

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A mixed LPDDR2 impedance calibration technique exploiting 28nm Fully-Depleted SOI Back-Biasing von Soussan, D., Valentian, A., Majcherczak, S., Belleville, M.

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A low jitter active body-biasing control-based output buffer in 65nm PD-SOI von Soussan, D, Majcherczak, S, Valentian, A, Belleville, M

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GeOI and SOI 3D monolithic cell integrations for high density applications von Batude, P., Vinet, M., Pouydebasque, A., Le Royer, C., Previtali, B., Tabone, C., Clavelier, L., Michaud, S., Valentian, A., Thomas, O., Rozeau, O., Coudrain, P., Leyris, C., Romanjek, K., Garros, X., Sanchez, L., Baud, L., Roman, A., Carron, V., Grampeix, H., Augendre, E., Toffoli, A., Allain, F., Grosgeorges, P., Mazzochi, V., Tosti, L., Andrieu, F., Hartmann, J.-M., Lafond, D., Deleonibus, S., Faynot, O.

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Ultra-Wide Voltage Range designs in Fully-Depleted Silicon-On-Insulator FETs von Beigne, E., Valentian, A., Giraud, B., Thomas, O., Benoist, T., Thonnart, Y., Bernard, S., Moritz, G., Billoint, O., Maneglia, Y., Flatresse, P., Noel, J.P., Abouzeid, F., Pelloux-Prayer, B., Grover, A., Clerc, S., Roche, P., Le Coz, J., Engels, S., Wilson, R.

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Gate bias circuit for an SCCMOS power switch achieving maximum leakage reduction von Valentian, A., Beigne, E.

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Integration and Frequency Dependent Parametric Modeling of Through Silicon via Involved in High Density 3D Chip Stacking von Cadix, Lionel, Fuchs, Christine, Rousseau, Maxime, Leduc, Patrick, Chaabouni, Hamed, Thuaire, Aurelie, Brocard, Melanie, Valentian, Alexandre, Farcy, Alexis, Bermond, Cedric, Sillon, Nicolas, Ancey, Pascal, Fléchet, Bernard

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Comparison of 65nm LP bulk and LP PD-SOI with adaptive power gate body bias for an LDPC codec von Le Coz, J, Flatresse, P, Engels, S, Valentian, A, Belleville, M, Raynaud, C, Croain, D, Urard, P

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