Heterogeneous FPGA Architecture Using Threshold Logic Gates for Improved Area, Power, and Performance von Wagle, Ankit, Vrudhula, Sarma

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Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA von Ma, Yufei, Cao, Yu, Vrudhula, Sarma, Seo, Jae-sun

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An ASIC Accelerator for QNN With Variable Precision and Tunable Energy Efficiency von Wagle, Ankit, Singh, Gian, Khatri, Sunil, Vrudhula, Sarma

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A New Approach to Clock Skewing for Area and Power Optimization of ASICs using Differential Flipflops and Local Clocking von Wagle, Ankit, Yang, Jinghua, Kulkarni, Niranjan, Vrudhula, Sarma

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A Novel ASIC Design Flow Using Weight-Tunable Binary Neurons as Standard Cells von Wagle, Ankit, Singh, Gian, Khatri, Sunil, Vrudhula, Sarma

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Performance Modeling for CNN Inference Accelerators on FPGA von Ma, Yufei, Cao, Yu, Vrudhula, Sarma, Seo, Jae-Sun

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Automatic Compilation of Diverse CNNs Onto High-Performance FPGA Accelerators von Ma, Yufei, Cao, Yu, Vrudhula, Sarma, Seo, Jae-Sun

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Design Considerations for Energy-Efficient and Variation-Tolerant Nonvolatile Logic von Yang, Jinghua, Dengi, Aykut, Vrudhula, Sarma

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A Mixed-Signal Quantized Neural Network Accelerator Using Flash Transistors von Scott, Kyler R., Lee, Cheng-Yen, Khatri, Sunil P., Vrudhula, Sarma

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Fully parallel write/read in resistive synaptic array for accelerating on-chip learning von Gao, Ligang, Wang, I-Ting, Chen, Pai-Yu, Vrudhula, Sarma, Seo, Jae-sun, Cao, Yu, Hou, Tuo-Hung, Yu, Shimeng

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The Impact of NBTI Effect on Combinational Circuit: Modeling, Simulation, and Analysis von Wenping Wang, Shengqi Yang, Bhardwaj, S., Vrudhula, S., Liu, F., Yu Cao

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Temperature-Aware DVFS for Hard Real-Time Applications on Multicore Processors von Hanumaiah, V., Vrudhula, S.

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CAMDNN: Content-Aware Mapping of a Network of Deep Neural Networks on Edge MPSoCs von Heidari, Soroush, Ghasemi, Mehdi, Kim, Young Geun, Wu, Carole-Jean, Vrudhula, Sarma

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Battery modeling for energy aware system design von Rao, R., Vrudhula, S., Rakhmatov, D.N.

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Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops von Kulkarni, Niranjan, Jinghua Yang, Jae-Sun Seo, Vrudhula, Sarma

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CIDAN-XE: Computing in DRAM with Artificial Neurons von Singh, Gian, Wagle, Ankit, Khatri, Sunil, Vrudhula, Sarma

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Identification of Threshold Functions and Synthesis of Threshold Networks von Gowda, Tejaswi, Vrudhula, Sarma, Kulkarni, Niranjan, Berezowski, Krzysztof

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Energy-Efficient Operation of Multicore Processors by DVFS, Task Migration, and Active Cooling von Hanumaiah, Vinay, Vrudhula, Sarma

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Predictive Modeling of the NBTI Effect for Reliable Design von Bhardwaj, S., Wenping Wang, Vattikonda, R., Cao, Y., Vrudhula, S.

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Parallel Architecture With Resistive Crosspoint Array for Dictionary Learning Acceleration von Kadetotad, Deepak, Zihan Xu, Mohanty, Abinash, Pai-Yu Chen, Binbin Lin, Jieping Ye, Vrudhula, Sarma, Shimeng Yu, Yu Cao, Jae-sun Seo

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