Treffer 1 - 15 von 15 für Suche 'VORA JIGAR J', Suchdauer: 0,53s Treffer weiter einschränken
  1. 1
    Cache array with reduced power consumption

    Cache array with reduced power consumption von Bunce, Paul A, Vora, Jigar J, Davis, John D, Henderson, Diana M

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  2. 2
    Cache array with reduced power consumption

    Cache array with reduced power consumption von Bunce, Paul A, Vora, Jigar J, Davis, John D, Henderson, Diana M

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  3. 3
    High frequency write through memory device

    High frequency write through memory device von DAVIS JOHN D, VORA JIGAR J, CHAN YUEN H, BUNCE PAUL A, HENDERSON DIANA M

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  4. 4
    CACHE ARRAY WITH REDUCED POWER CONSUMPTION

    CACHE ARRAY WITH REDUCED POWER CONSUMPTION von DAVIS JOHN D, VORA JIGAR J, BUNCE PAUL A, HENDERSON DIANA M

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  5. 5
    Increasing memory operating frequency

    Increasing memory operating frequency von DAVIS JOHN D, VORA JIGAR J, BUNCE PAUL A, HENDERSON DIANA M

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  6. 6
    INCREASING MEMORY OPERATING FREQUENCY

    INCREASING MEMORY OPERATING FREQUENCY von DAVIS JOHN D, VORA JIGAR J, BUNCE PAUL A, HENDERSON DIANA M

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  7. 7
    HIGH FREQUENCY MEMORY

    HIGH FREQUENCY MEMORY von DAVIS JOHN D, VORA JIGAR J, CHAN YUEN H, BUNCE PAUL A, HENDERSON DIANA M

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  8. 8
    CACHE ARRAY WITH REDUCED POWER CONSUMPTION

    CACHE ARRAY WITH REDUCED POWER CONSUMPTION von DAVIS JOHN D, VORA JIGAR J, BUNCE PAUL A, HENDERSON DIANA M

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  9. 9
    Port enable signal generation for gating a memory array device output

    Port enable signal generation for gating a memory array device output von DAVIS JOHN D, VORA JIGAR J, BUNCE PAUL A, HENDERSON DIANA M

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  10. 10
    Jam latch for latching memory array output data

    Jam latch for latching memory array output data von Bunce, Paul A, Davis, John D, Henderson, Diana M, Vora, Jigar J

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  11. 11
    Jam latch for latching memory array output data

    Jam latch for latching memory array output data von DAVIS JOHN D, VORA JIGAR J, BUNCE PAUL A, HENDERSON DIANA M

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  12. 12
    Split voltage level restore and evaluate clock signals for memory address decoding

    Split voltage level restore and evaluate clock signals for memory address decoding von DAVIS JOHN D, VORA JIGAR J, BUNCE PAUL A, HENDERSON DIANA M

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  13. 13
    Split voltage level restore and evaluate clock signals for memory address decoding

    Split voltage level restore and evaluate clock signals for memory address decoding von Bunce, Paul A, Davis, John D, Henderson, Diana M, Vora, Jigar J

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  14. 14
    Internal bypassing of memory array devices

    Internal bypassing of memory array devices von DAVIS JOHN D, VORA JIGAR J, BUNCE PAUL A, HENDERSON DIANA M

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  15. 15
    Internal bypassing of memory array devices

    Internal bypassing of memory array devices von Bunce, Paul A, Davis, John D, Henderson, Diana M, Vora, Jigar J

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