Interconnect limits on gigascale integration (GSI) in the 21st century von Davis, J.A., Meindl, J.D., Venkatesan, R., Kaloyeros, A., Beylansky, M., Souri, S.J., Banerjee, K., Saraswat, K.C., Rahman, A., Reif, R.

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Compact distributed RLC interconnect models - part IV: unified models for time delay, crosstalk, and repeater insertion von Venkatesan, R., Davis, J.A., Meindl, J.D.

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Optimal global interconnects for GSI von Naeemi, A., Venkatesan, R., Meindl, J.D.

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Compact distributed RLC interconnect models - part III: transients in single and coupled lines with capacitive load termination von Venkatesan, R., Davis, J.A., Meindl, J.D.

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Impact of three-dimensional architectures on interconnects in gigascale integration von Joyner, J.W., Venkatesan, R., Zarkesh-Ha, P., Davis, J.A., Meindl, J.D.

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Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI) von Venkatesan, R., Davis, J.A., Bowman, K.A., Meindl, J.D.

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A physical model for the transient response of capacitively loaded distributed rlc interconnects von Venkatesan, Raguraman, Davis, Jeffrey A., Meindl, James D.

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GENERATING AN ASSOCIATION DATASET FOR MANIPULATING A PHOTOMASK PATTERN von BROCKMAN, Christopher, AGARWAL, Diwakar, VENKATESAN, Raguraman, DHANANJAY VINJAMUR, Raghunathan

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Interconnect limits on gigascale integration (GSI) in the 21st century: The Limits of Semiconductor Technology von DAVIS, Jeffrey A, VENKATESAN, Raguraman, KALOYEROS, Alain, BEYLANSKY, Michael, SOURI, Shukri J, BANERJEE, Kaustav, SARASWAT, Krishna C, RAHMAN, Arifur, REIF, Rafael, MEINDL, James D

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A physical model for the transient response of capacitively loaded distributed RLC interconnects von Venkatesan, R., Davis, J.A., Meindl, J.D.

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Mask design and OPC for device manufacture von HOOKER KEVIN J, KIM SUNGWON, SINGH VIVEK, BAIDYA BIKRAM, JEONG SEONGTAE, OGADHOH SHEM, VENKATESAN RAGURAMAN, HU BIN, NARENDRA ATKAR PRASAD

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MASK DESIGN AND OPC FOR DEVICE MANUFACTURE von HOOKER KEVIN J, KIM SUNGWON, SINGH VIVEK, BAIDYA BIKRAM, JEONG SEONGTAE, OGADHOH SHEM, VENKATESAN RAGURAMAN, HU BIN, NARENDRA ATKAR PRASAD

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Mask design and OPC for device manufacture von HOOKER KEVIN J, KIM SUNGWON, ATKAR PRASAD NARENDRA, SINGH VIVEK, BAIDYA BIKRAM, JEONG SEONGTAE, OGADHOH SHEM, VENKATESAN RAGURAMAN, HU BIN

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Impact of size effects on the resistivity of copper wires and consequently the design and performance of metal interconnect networks von Sarvari, R., Naeemi, A., Venkatesan, R., Meindl, J.D.

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MASK DESIGN AND OPC FOR DEVICE MANUFACTURE von HOOKER KEVIN J, KIM SUNGWON, ATKAR PRASAD NARENDRA, SINGH VIVEK, BAIDYA BIKRAM, JEONG SEONGTAE, OGADHOH SHEM, VENKATESAN RAGURAMAN, HU BIN

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System-on-a-chip global interconnect optimization von Naeemi, A., Venkatesan, R., Meindl, J.D.

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Performance enhancement through optimal n-tier multilevel interconnect architectures von Venkatesan, R., Davis, J.A., Meindl, J.D.

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Time delay, crosstalk and repeater insertion models for high performance SoC's von Venkatesan, R., Davis, J.A., Meindl, J.D.

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Mask design and opc for device manufacture von ATKAR, PRASAD NARENDRA, KIM, SUNGWON, OGADHOH, SHEM, BAIDYA, BIKRAM, JEONG, SEONGTAE, HU, BIN, VENKATESAN, RAGURAMAN, HOOKER, KEVIN J, SINGH, VIVEK

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Minimum power and area n-tier multilevel interconnect architectures using optimal repeater insertion von Venkatesan, Raguraman, Davis, Jeffrey A., Bowman, Keith A., Meindl, James D.

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