The Oracle Sparc T5 16-Core Processor Scales to Eight Sockets von Feehrer, J., Jairath, S., Loewenstein, P., Sivaramakrishnan, R., Smentek, D., Turullols, S., Vahidsafa, A.

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SPARC M7: A 20 nm 32-Core 64 MB L3 Cache Processor von Konstadinidis, Georgios K., Li, Hongping Penny, Schumacher, Francis, Krishnaswamy, Venkat, Cho, Hoyeol, Dash, Sudesna, Masleid, Robert P., Zheng, Chaoyang, Lin, Yuanjung David, Loewenstein, Paul, Park, Heechoul, Srinivasan, Vijay, Huang, Dawei, Hwang, Changku, Hsu, Wenjay, McAllister, Curtis, Brooks, Jeff, Pham, Ha, Turullols, Sebastian, Yanggong, Yifan, Golla, Robert, Smith, Alan P., Vahidsafa, Ali

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High speed functional test vectors in low power test conditions of a digital integrated circuit von Vahidsafa, Ali

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Distributed mechanism for clock and reset control in a microprocessor von Vahidsafa Ali

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ROTATIONAL SYNCHRONIZER CIRCUIT FOR METASTABLITY RESOLUTION von MASLEID, Robert, P, VAHIDSAFA, Ali

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Drift compensation for a real time clock circuit von Vahidsafa Ali

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HIGH SPEED FUNCTIONAL TEST VECTORS IN LOW POWER TEST CONDITIONS OF A DIGITAL INTEGRATED CIRCUIT von Vahidsafa Ali

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DISTRIBUTED MECHANISM FOR CLOCK AND RESET CONTROL IN A MICROPROCESSOR von Vahidsafa Ali

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Mixing of low speed and high speed clocks to improve test precision of a digital integrated circuit von Vahidsafa Ali

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DRIFT COMPENSATION FOR A REAL TIME CLOCK CIRCUIT von VAHIDSAFA ALI

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MIXING OF LOW SPEED AND HIGH SPEED CLOCKS TO IMPROVE TEST PRECISION OF A DIGITAL INTEGRATED CIRCUIT von VAHIDSAFA ALI

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METHOD FOR MIGRATING CPU STATE FROM AN INOPERABLE CORE TO A SPARE CORE von Vahidsafa, Ali, Onufer, Gregory, Jordan, Paul, Lewis, James

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Hybrid hardwired/programmable reset sequence controller von VAHIDSAFA ALI

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Cycle deterministic functional testing of a chip with asynchronous clock domains von Vahidsafa, Ali, Anandakumar, Sriram

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Method and apparatus for synchronizing the time reference of a dynamically activated processor to the system time reference von VAHIDSAFA ALI

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Method for migrating CPU state from an inoperable core to a spare core von Vahidsafa, Ali, Onufer, Gregory, Jordan, Paul, Lewis, James

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METHOD AND APPARATUS FOR SYNCHRONIZING THE TIME REFERENCE OF A DYNAMICALLY ACTIVATED PROCESSOR TO THE SYSTEM TIME REFERENCE von VAHIDSAFA ALI

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HYBRID HARDWIRED/PROGRAMMABLE RESET SEQUENCE CONTROLLER von VAHIDSAFA ALI

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MEMORY MIGRATION IN PRESENCE OF LIVE MEMORY TRAFFIC von VAHIDSAFA, Ali, CHEUNG, Connie, Wai Mun

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METHOD FOR MIGRATING CPU STATE FROM AN INOPERABLE CORE TO A SPARE CORE von Vahidsafa, Ali, Onufer, Gregory, Jordan, Paul, Lewis, James

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