An Overview of Static Pipelining von Finlayson, I., Gang-Ryung Uh, Whalley, D., Tyson, G.

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Compiler transformations for effectively exploiting a zero overhead loop buffer von Uh, Gang-Ryung, Wang, Yuhong, Whalley, David, Jinturkar, Sanjay, Paek, Yunheung, Cao, Vincent, Burns, Chris

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Branch elimination by condition merging von Kreahling, William C., Whalley, David, Bailey, Mark W., Yuan, Xin, Uh, Gang-Ryung, van Engelen, Robert

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Improving Low Power Processor Efficiency with Static Pipelining von Finlayson, I., Gang-Ryung Uh, Whalley, D., Tyson, G.

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Tailoring Software Pipelining for Effective Exploitation of Zero Overhead Loop Buffer von Uh, Gang-Ryung

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Effectively exploiting indirect jumps von Uh, Gang-Ryung, Whalley, David B.

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Instruction Re-selection for Iterative Modulo Scheduling on High Performance Multi-issue DSPs von Cho, Doosan, Ravi, Ayyagari, Uh, Gang-Ryung, Paek, Yunheung

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Efficient and effective branch reordering using profile data von Yang, Minghui, Uh, Gang-Ryung, Whalley, David B.

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Improving processor efficiency by statically pipelining instructions von Finlayson, Ian, Davis, Brandon, Gavin, Peter, Uh, Gang-Ryung, Whalley, David, Själander, Magnus, Tyson, Gary

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Coalescing conditional branches into efficient indirect jumps von Uh, Gang-Ryung, Whalley, David B.

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Preprocessing Strategy for Effective Modulo Scheduling on Multi-issue Digital Signal Processors von Odersky, Martin, Krishnamurthi, Shriram

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Techniques for Effectively Exploiting a Zero Overhead Loop Buffer von Uh, Gang-Ryung, Wang, Yuhong, Whalley, David, Jinturkar, Sanjay, Burns, Chris, Cao, Vincent

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Improving performance by branch reordering von Yang, Minghui, Uh, Gang-Ryung, Whalley, David B

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Effective exploitation of a zero overhead loop buffer von Uh, Gang-Ryung, Wang, Yuhong, Whalley, David, Jinturkar, Sanjay, Burns, Chris, Cao, Vincent

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Tuning the WCET of embedded applications von WANKANG ZHAO, KULKARNI, Prasad, WHALLEY, David, HEALY, Christopher, MUELLER, Frank, UH, Gang-Ryung

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Improving performance by branch reordering von Yang, Minghui, Uh, Gang-Ryung, Whalley, David B.

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Optimizing Transfers of Control in the Static Pipeline Architecture von Baird, Ryan, Gavin, Peter, Själander, Magnus, Whalley, David, Uh, Gang-Ryung

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Session details: Compiler optimizations von Uh, Gang-Ryung

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Branch elimination via multi-variable condition merging von KREAHLING, William, WHALLEY, David, BAILEY, Mark, XIN YUAN, UH, Gang-Ryung, VAN ENGELEN, Robert

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Branch Elimination via Multi-variable Condition Merging von Kreahling, William, Whalley, David, Bailey, Mark, Yuan, Xin, Uh, Gang-Ryung, van Engelen, Robert

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