Expectation values in two-component relativistic theories von Seino, Junji, Uesugi, Wataru, Hada, Masahiko

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Embedded SRAM and Cortex-M0 Core Using a 60-nm Crystalline Oxide Semiconductor von Tamura, Hikaru, Kato, Kiyoshi, Ishizu, Takahiko, Uesugi, Wataru, Isobe, Atsuo, Tsutsui, Naoaki, Suzuki, Yasutaka, Okazaki, Yutaka, Maehashi, Yukio, Koyama, Jun, Yamamoto, Yoshitaka, Yamazaki, Shunpei, Fujita, Masahiro, Myers, James, Korpinen, Pekka

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Embedded Memory and ARM Cortex-M0 Core Using 60-nm C-Axis Aligned Crystalline Indium-Gallium-Zinc Oxide FET Integrated With 65-nm Si CMOS von Onuki, Tatsuya, Uesugi, Wataru, Isobe, Atsuo, Ando, Yoshinori, Okamoto, Satoru, Kato, Kiyoshi, Tri Rung Yew, Wu, J. Y., Chi Chang Shuai, Shao Hui Wu, Myers, James, Doppler, Klaus, Fujita, Masahiro, Yamazaki, Shunpei

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Embedded Memory and ARM Cortex-M0 Core Using 60-nm C-Axis Aligned Crystalline Indiu–Galliu–Zinc Oxide FET Integrated With 65-nm Si CMOS von Onuki, Tatsuya, Uesugi, Wataru, Isobe, Atsuo, Ando, Yoshinori, Okamoto, Satoru, Kato, Kiyoshi, Tri Rung Yew, Wu, J Y, Chi Chang Shuai, Shao Hui Wu, Myers, James, Doppler, Klaus, Fujita, Masahiro, Yamazaki, Shunpei

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Embedded SRAM and Cortex-M0 Core with Backup Circuits using a 60-nm Crystalline Oxide Semiconductor for Power Gating von Tamura, Hikaru, Kato, Kiyoshi, Ishizu, Takahiko, Uesugi, Wataru, Isobe, Atsuo, Tsutsui, Naoaki, Suzuki, Yasutaka, Okazaki, Yutaka, Maehashi, Yukio, Koyama, Jun, Yamamoto, Yoshitaka, Yamazaki, Shunpei, Fujita, Masahiro, Myers, James, Korpinen, Pekka

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State retention flip flop architectures with different tradeoffs using crystalline indium gallium zinc oxide transistors implemented in a 32-bit normally-off microprocessor von Sjökvist, Niclas, Ohmaru, Takuro, Isobe, Atsuo, Tsutsui, Naoaki, Tamura, Hikaru, Uesugi, Wataru, Ishizu, Takahiko, Onuki, Tatsuya, Ohshima, Kazuaki, Matsuzaki, Takanori, Mimura, Hidetoshi, Hirose, Atsushi, Suzuki, Yasutaka, Ieda, Yoshinori, Atsumi, Tomoaki, Shionoiri, Yutaka, Kato, Kiyoshi, Goto, Gensuke, Koyama, Jun, Fujita, Masahiro, Yamazaki, Shunpei

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Logic circuit, processing unit, electronic component, and electronic device von Uesugi, Wataru, Tamura, Hikaru, Isobe, Atsuo

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Semiconductor device von UESUGI WATARU

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LOGIC CIRCUIT, PROCESSING UNIT, ELECTRONIC COMPONENT, AND ELECTRONIC DEVICE von ISOBE, Atsuo, TAMURA, Hikaru, UESUGI, Wataru

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Word line driver comprising NAND circuit von Ishizu, Takahiko, Uesugi, Wataru

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Logic circuit, processing unit, electronic component, and electronic device von Uesugi, Wataru, Tamura, Hikaru, Isobe, Atsuo

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Zero Area Overhead State Retention Flip Flop Utilizing Crystalline In-Ga-Zn Oxide Technology von Sjokvist, Niclas, Ohmaru, Takuro, Furutani, Kazuma, Isobe, Atsuo, Tsutsui, Naoaki, Tamura, Hikaru, Uesugi, Wataru, Ishizu, Takahiko, Onuki, Tatsuya, Ohshima, Kazuaki, Matsuzaki, Takanori, Mimura, Hidetoshi, Hirose, Atsushi, Suzuki, Yasutaka, Ieda, Yoshinori, Atsumi, Tomoaki, Shionoiri, Yutaka, Kato, Kiyoshi, Goto, Gensuke, Koyama, Jun, Fujita, Masahiro, Yamazaki, Shunpei

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Semiconductor device, electronic component, and electronic device von Uesugi, Wataru, Onuki, Tatsuya

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Level-shift circuit, driver IC, and electronic device von Uesugi, Wataru, Osada, Takeshi

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SEMICONDUCTOR DEVICE von UESUGI WATARU

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SEMICONDUCTOR DEVICE von UESUGI WATARU

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Magnetic Interaction in Ce_<1-x>Gd_xRu_2Ge_2 von Kusumoto, Toshiaki, Uesugi, Wataru, Watanuki, Ryuta, Suzuki, Kazuya

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SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, AND ELECTRONIC DEVICE von ONUKI Tatsuya, UESUGI Wataru

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LOGIC CIRCUIT, PROCESSING UNIT, ELECTRONIC COMPONENT, AND ELECTRONIC DEVICE von ISOBE, Atsuo, TAMURA, Hikaru, UESUGI, Wataru

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Microcontroller System von TAMURA Hikaru, UESUGI Wataru

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