Treffer 1 - 7 von 7 für Suche 'Tziantzioulis, Georgios', Suchdauer: 0,41s Treffer weiter einschränken
  1. 1
    Temporal Approximate Function Memoization

    Temporal Approximate Function Memoization von Tziantzioulis, Georgios, Hardavellas, Nikos, Campanoni, Simone

    Veröffentlicht in IEEE MICRO

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  2. 2
    OPDB: A Scalable and Modular Design Benchmark

    OPDB: A Scalable and Modular Design Benchmark von Tziantzioulis, Georgios, Chang, Ting-Jung, Balkind, Jonathan, Tu, Jinzheng, Gao, Fei, Wentzlaff, David


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  3. 3
    OpenPiton at 5: A Nexus for Open and Agile Hardware Design

    OpenPiton at 5: A Nexus for Open and Agile Hardware Design von Balkind, Jonathan, Chang, Ting-Jung, Jackson, Paul J., Tziantzioulis, Georgios, Li, Ang, Gao, Fei, Lavrov, Alexey, Chirkov, Grigory, Tu, Jinzheng, Shahrad, Mohammad, Wentzlaff, David

    Veröffentlicht in IEEE MICRO

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  4. 4
    CIFER: A Cache-Coherent 12nm 16mm2 SoC With Four 64-Bit RISC-V Application Cores, 18 32-Bit RISC-V Compute Cores, and a 1541 LUT6/mm2 Synthesizable eFPGA

    CIFER: A Cache-Coherent 12nm 16mm2 SoC With Four 64-Bit RISC-V Application Cores, 18 32-Bit RISC-V Compute Cores, and a 1541 LUT6/mm2 Synthesizable eFPGA von Li, Ang, Chang, Ting-Jung, Gao, Fei, Ta, Tuan, Tziantzioulis, Georgios, Ou, Yanghui, Wang, Moyang, Tu, Jinzheng, Xu, Kaifeng, Jackson, Paul, Ning, August, Chirkov, Grigory, Orenes-Vera, Marcelo, Agwa, Shady, Yan, Xiaoyu, Tang, Eric, Balkind, Jonathan, Batten, Christopher, Wentzlaff, David


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  5. 5
    CIFER: A Cache-Coherent 12-nm 16-mm 2 SoC With Four 64-Bit RISC-V Application Cores, 18 32-Bit RISC-V Compute Cores, and a 1541 LUT6/mm 2 Synthesizable eFPGA

    CIFER: A Cache-Coherent 12-nm 16-mm 2 SoC With Four 64-Bit RISC-V Application Cores, 18 32-Bit RISC-V Compute Cores, and a 1541 LUT6/mm 2 Synthesizable eFPGA von Li, Ang, Chang, Ting-Jung, Gao, Fei, Ta, Tuan, Tziantzioulis, Georgios, Ou, Yanghui, Wang, Moyang, Tu, Jinzheng, Xu, Kaifeng, Jackson, Paul, Ning, August, Chirkov, Grigory, Orenes-Vera, Marcelo, Agwa, Shady, Yan, Xiaoyu, Tang, Eric, Balkind, Jonathan, Batten, Christopher, Wentzlaff, David


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  6. 6
    CIFER: A Cache-Coherent 12-nm 16-mm2 SoC With Four 64-Bit RISC-V Application Cores, 18 32-Bit RISC-V Compute Cores, and a 1541 LUT6/mm2 Synthesizable eFPGA

    CIFER: A Cache-Coherent 12-nm 16-mm2 SoC With Four 64-Bit RISC-V Application Cores, 18 32-Bit RISC-V Compute Cores, and a 1541 LUT6/mm2 Synthesizable eFPGA von Ang, Li, Ting-Jung, Chang, Gao, Fei, Ta, Tuan, Tziantzioulis, Georgios, Ou, Yanghui, Wang, Moyang, Tu, Jinzheng, Xu, Kaifeng, Jackson, Paul, August, Ning, Chirkov, Grigory, Orenes-Vera, Marcelo, Agwa, Shady, Yan, Xiaoyu, Tang, Eric, Balkind, Jonathan, Batten, Christopher, Wentzlaff, David


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  7. 7
    Significance driven computation on next-generation unreliable platforms

    Significance driven computation on next-generation unreliable platforms von Karakonstantis, Georgios, Bellas, Nikolaos, Antonopoulos, Christos, Tziantzioulis, Georgios, Gupta, Vaibhav, Roy, Kaushik


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