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A highly scaled, high performance 45 nm bulk logic CMOS technology with 0.242 μm2 SRAM cell von Kuan-Lun Cheng, Wu, C.C., Wang, Y.P., Lin, D.W., Chu, C.M., Tarng, Y.Y., Lu, S.Y., Yang, S.J., Hsieh, M.H., Liu, C.M., Fu, S.P., Chen, J.H., Lin, C.T., Lien, W.Y., Huang, H.Y., Wang, P.W., Lin, H.H., Lee, D.Y., Huang, M.J., Nieh, C.F., Lin, L.T., Chen, C.C., Chang, W., Chiu, Y.H., Wang, M.Y., Yeh, C.H., Chen, F.C., Chang, Y.H., Wang, S.C., Hsieh, H.C., Lei, M.D., Goto, K., Tao, H.J., Cao, M., Tuan, H.C., Diaz, C.H., Mii, Y.J., Wu, C.M.

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