Soft error interception latch: double node charge sharing SEU tolerant design von Katsarou, K, Tsiatouhas, Y

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A Robust and Reconfigurable Multi-mode Power Gating Architecture von Zhang, Z, Kavousianos, X, Chakrabarty, K, Tsiatouhas, Y

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A Design Technique for Energy Reduction in NORA CMOS Logic von Limniotis, K., Tsiatouhas, Y., Haniotakis, T., Arapoyanni, A.

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Testable Designs of Multiple Precharged Domino Circuits von Haniotakis, T., Tsiatouhas, Y., Nikolos, D., Efstathiou, C.

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A Built-In Voltage Measurement Technique for the Calibration of RF Mixers von Liaperdos, J., Arapoyanni, A., Tsiatouhas, Y.

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A Circuit for Concurrent Detection of Soft and Timing Errors in Digital CMOS ICs von Matakias, S, Tsiatouhas, Y, Arapoyanni, A, Haniotakis, Th

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A Stress-Relaxed Negative Voltage-Level Converter von Tsiatouhas, Y.E.

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A design for testability technique for mixed-signal differential circuits von Dermentzoglou, L, Tsiatouhas, Y, Arapoyanni, A

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A Design for Testability Scheme for CMOS LC-Tank Voltage Controlled Oscillators von Dermentzoglou, L, Tsiatouhas, Y, Arapoyanni, A

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A high-density DRAM cell with built-in gain stage von Kamoulakos, G., Tsiatouhas, Y., Chrisanthopoulos, A., Arapoyanni, A.

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Timing error tolerance in nanometer ICs von Valadimas, S, Tsiatouhas, Y, Arapoyanni, A

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Management of charge pump circuits von Kamoulakos, G., Chrisanthopoulos, A., Tsiatouhas, Y., Arapoyanni, A.

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A Current Mode, Parallel, Two-Rail Code Checker von Matakias, Sotirios, Tsiatouhas, Yiorgos, Haniotakis, Themistoklis, Arapoyanni, Angela

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Single event upset tolerance in flip-flop based microprocessor cores von Valadimas, S., Tsiatouhas, Y., Arapoyanni, A., Evans, A.

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Signature Analysis for Testing, Diagnosis, and Repair of Multi-mode Power Switches von Zhaobo Zhang, Kavousianos, X., Yan Luo, Tsiatouhas, Y., Chakrabarty, K.

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High fan-in differential current mirror logic von Tsiatouhas, Y., Arapoyanni, A.

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C-testable one-dimensional ILAs with respect to path delay faults: theory and applications von Haniotakis, Th, Tsiatouhas, Y., Nikolos, D.

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Robust test generation for transistor stuck-open faults in CMOS complex gates von TSIATOUHAS, Y., PASCHALIS, A., NIKOLOS, D., HALATSIS, C.

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Hierarchical robust test generation for CMOS circuit stuck-open faults von TSIATOUHAS, Y., HANIOTAKIS, TH, NIKOLOS, D., PASCHALIS, A., HALATSIS, C.

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Path delay fault testing of ICs with embedded intellectual property blocks von Nikolos, D., Haniotakis, T., Vergos, H.T., Tsiatouhas, Y.

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