Chip Optimization Through STI-Stress-Aware Placement Perturbations and Fill Insertion von Kahng, A.B., Sharma, P., Topaloglu, R.O.

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DOE-Based Extraction of CMP, Active and Via Fill Impact on Capacitances von Kahng, A.B., Topaloglu, R.O.

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Process Variation-Aware Multiple-Fault Diagnosis of Thermometer-Coded Current-Steering DACs von Topaloglu, R.O.

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Early, accurate and fast yield estimation through Monte Carlo-alternative probabilistic behavioral analog system simulations von Topaloglu, R.O.

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Standard Cell and Custom Circuit Optimization using Dummy Diffusions through STI Width Stress Effect Utilization von Topaloglu, R.O.

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Interconnect Matching Design Rule Inferring and Optimization through Correlation Extraction von Kahng, A.B., Topaloglu, R.O.

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Exploiting STI stress for performance von Kahng, A.B., Sharma, P., Topaloglu, R.O.

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A DFT approach for diagnosis and process variation-aware structural test of thermometer coded current steering DACs von Topaloglu, Rasit Onur, Orailoglu, Alex

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Energy-Minimization Model for Fill Synthesis von Topaloglu, R.O.

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Process Variation Characterization and Modeling of Nanoparticle Interconnects for Foldable Electronics von Topaloglu, R.O.

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Monte Carlo-Alternative Probabilistic Simulations for Analog Systems von Topaloglu, Rasit Onur

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A DOE Set for Normalization-Based Extraction of Fill Impact on Capacitances von Kahng, A.B., Topaloglu, R.O.

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Forward discrete probability propagation method for device performance characterization under process variations von Topaloglu, R.O., Orailoglu, A.

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On mismatch in the deep sub-micron era-from physics to circuits von Topaloglu, R.O., Orailoglu, A.

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