Design Time Optimization for Hardware Watermarking Protection of HDL Designs von Todorovich, Elías, Parrilla, L., García, Antonio, Morales, D. P., Castillo, E., Meyer-Baese, U.

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Introducing Programmable Logic to Undergraduate Engineering Students in a Digital Electronics Course von Todorovich, E., Marone, J. A., Vazquez, M.

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High Resolution FPGA DPWM Based on Variable Clock Phase Shifting von de Castro, Angel, Todorovich, Elias

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Improvements for the applicability of power-watermarking to embedded IP cores protection: e-coreIPP von Parrilla, L., Castillo, E., Todorovich, E., García, A., Morales, D.P., Botella, G.

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Genetic algorithms and fuzzy control: a practical synergism for industrial applications von Acosta, Gerardo, Todorovich, Elı́as

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Low-Power FSMs in FPGA: Encoding Alternatives von Sutter, G., Todorovich, E., Lopez-Buedo, S., Boemo, E.

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A Tool for Activity Estimation in FPGAs von Todorovich, E., Gilabert, M., Sutter, G., Lopez-Buedo, S., Boemo, E.

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DPWM based on FPGA clock phase shifting with time resolution under 100 ps von de Castro, A., Todorovich, E.

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A co-design methodology for processor-centric embedded systems with hardware acceleration using FPGA von Pedre, S., Krajnik, T., Todorovich, E., Borensztejn, P.

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Automated Signature Insertion in Combinational Logic Patterns for HDL IP Core Protection von Castillo, E., Parrilla, L., Garcia, A., Meyer-Baese, U., Botella, G., Lloris, A.

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Experiences applying OVM 2.0 to an 8B/10B RTL design von Cadenas, O., Todorovich, E.

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A Reconfigurable Prototyping Platform for Smart Sensor Networks von Hinkelmann, H., Reinhardt, A., Varyani, S., Glesner, M.

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A Reconfigurable Fpga-Based Architecture for Modular Nodes in Wireless Sensor Networks von Portilla, J., Riesgo, T., de Castro, A.

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TCL/TK for EDA Tools von Todorovich, E., Cadenas, O.

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Simulation-Based Approach for Evaluating On-Chip Interconnect Architectures von Suboh, S., Bakhouya, M., Lopez-Buedo, S., El-Ghazawi, T.

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Generic construction of monitors for Floating Point Unit designs von Goni, O., Todorovich, E., Cadenas, O.

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AES-128 Cipher. High Speed, Low Cost FPGA Implementation von Liberatori, M., Otero, F., Bonadero, J.C., Castineira, J.

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Integrated Hardware/Software Codesign for Heterogeneous Computing Systems von Lam, Y.M., Coutinho, J.G.F., Luk, W.

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Comparative Analysis of High Level Programming for Reconfigurable Computers: Methodology and Empirical Study von El-Araby, E., Taher, M., Abouellail, M., El-Ghazawi, T., Newby, G.B.

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Memory Optimized Architecture for Efficient Gauss-Jordan Matrix Inversion von de Matos, G.M., Neto, H.C.

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