Active Guardband Management in Power7+ to Save Energy and Maintain Reliability von Lefurgy, C. R., Drake, A. J., Floyd, M. S., Allen-Ware, M. S., Brock, B., Tierno, J. A., Carter, J. B., Berry, R. W.

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Introducing the Adaptive Energy Management Features of the Power7 Chip von Floyd, M, Allen-Ware, M, Rajamani, K, Brock, B, Lefurgy, C, Drake, A J, Pesantez, L, Gloekler, T, Tierno, J A, Bose, P, Buyuktosunoglu, A

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A 28 GHz Hybrid PLL in 32 nm SOI CMOS von Ferriss, Mark, Rylyakov, Alexander, Tierno, Jose A., Ainspan, Herschel, Friedman, Daniel J.

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A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing von Sadhu, Bodhisatwa, Ferriss, Mark A., Natarajan, Arun S., Yaldiz, Soner, Plouchart, Jean-Olivier, Rylyakov, Alexander V., Valdes-Garcia, Alberto, Parker, Benjamin D., Babakhani, Aydin, Reynolds, Scott, Li, Xin, Pileggi, Larry, Harjani, Ramesh, Tierno, Jose, Friedman, Daniel

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A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOI CMOS von Agrawal, A., Bulzacchelli, J. F., Dickson, T. O., Liu, Y., Tierno, J. A., Friedman, D. J.

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An Integral Path Self-Calibration Scheme for a Dual-Loop PLL von Ferriss, M., Plouchart, J., Natarajan, A., Rylyakov, A., Parker, B., Tierno, J., Babakhani, A., Yaldiz, S., Valdes-Garcia, A., Sadhu, B., Friedman, D.

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An Adaptively Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 Gigahertz von Singh, Montek, Tierno, Jose A, Rylyakov, Alexander, Rylov, Sergey, Nowick, Steven M

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Correction to "A Linearized, Low Phase Noise VCO Based 25 GHz PLL With Autonomic Biasing" von Sadhu, Bodhisatwa, Ferriss, Mark A., Natarajan, Arun S., Yaldiz, Soner, Plouchart, Jean-Olivier, Rylyakov, Alexander V., Valdes-Garcia, Alberto, Parker, Benjamin D., Babakhani, Aydin, Reynolds, Scott, Li, Xin, Pileggi, Larry, Harjani, Ramesh, Tierno, Jose A., Friedman, Daniel

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A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons von Seo, J., Brezzo, B., Liu, Y., Parker, B. D., Esser, S. K., Montoye, R. K., Rajendran, B., Tierno, J. A., Chang, L., Modha, D. S., Friedman, D. J.

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A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI von Tierno, J.A., Rylyakov, A.V., Friedman, D.J.

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A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology von Dickson, Timothy O., Yong Liu, Rylov, Sergey V., Agrawal, Ankur, Seongwon Kim, Ping-Hsuan Hsieh, Bulzacchelli, John F., Ferriss, Mark, Ainspan, Herschel A., Rylyakov, Alexander, Parker, Benjamin D., Beakes, Michael P., Baks, Christian, Lei Shan, Young Kwark, Tierno, Jose A., Friedman, Daniel J.

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Integrated transversal equalizers in high-speed fiber-optic systems von Hui Wu, Tierno, J.A., Pepeljugoski, P., Schaub, J., Gowda, S., Kash, J.A., Hajimiri, A.

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Performance of Simulated Annealing Algorithm in Equalized Multimode Fiber Links With Linear Equalizers von Pepeljugoski, P.K., Tierno, J.A., Risteski, A., Reynolds, S.K., Schares, L.

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A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS von Plouchart, J.-O., Yaldiz, S., Pileggi, L., Harjani, R., Reynolds, S., Tierno, J. A., Friedman, D., Ferriss, M., Natarajan, A. S., Valdes-Garcia, A., Sadhu, B., Rylyakov, A., Parker, B. D., Beakes, M., Babakhani, A.

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A 1.4 pJ/bit, Power-Scalable 1612 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology von Dickson, Timothy O, Liu, Yong, Rylov, Sergey V, Agrawal, Ankur, Kim, Seongwon, Hsieh, Ping-Hsuan, Bulzacchelli, John F, Ferriss, Mark, Ainspan, Herschel A, Rylyakov, Alexander, Parker, Benjamin D, Beakes, Michael P, Baks, Christian, Shan, Lei, Kwark, Young, Tierno, Jose A, Friedman, Daniel J

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Clock Frequency Limiter von Tierno, Jose A, Rao, Ajay M

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Clock frequency limiter von Tierno, Jose A, Rao, Ajay M

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CLOCK FREQUENCY LIMITER von RAO, Ajay M, TIERNO, Jose A

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Clock Frequency Limiter von Tierno, Jose A, Rao, Ajay M

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Data Detection on Serial Communication Links von Gupta, Sumeet, Varma, Vishal, Shah, Dhaval H, Tierno, Jose A, Maheshwari, Sanjeev K

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