VeriGen: A Large Language Model for Verilog Code Generation von Thakur, Shailja, Ahmad, Baleegh, Pearce, Hammond, Tan, Benjamin, Dolan-Gavitt, Brendan, Karri, Ramesh, Garg, Siddharth

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On Hardware Security Bug Code Fixes by Prompting Large Language Models von Ahmad, Baleegh, Thakur, Shailja, Tan, Benjamin, Karri, Ramesh, Pearce, Hammond

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CANOA: CAN Origin Authentication through Power Side-channel Monitoring von Thakur, Shailja, Moreno, Carlos, Fischmeister, Sebastian

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(Security) Assertions by Large Language Models von Kande, Rahul, Pearce, Hammond, Tan, Benjamin, Dolan-Gavitt, Brendan, Thakur, Shailja, Karri, Ramesh, Rajendran, Jeyavijayan

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Security and Interpretability in Automotive Systems von Thakur, Shailja

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Security and Interpretability in Automotive Systems von Thakur, Shailja

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Security and Interpretability in Automotive Systems von Thakur, Shailja

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A generalizable saliency map-based interpretation of model outcome von Thakur, Shailja, Fischmeister, Sebastian

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Can EDA Tool Feedback Improve Verilog Generation by LLMs? von Blocklove, Jason, Thakur, Shailja, Tan, Benjamin, Pearce, Hammond, Garg, Siddharth, Karri, Ramesh

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Fixing Hardware Security Bugs with Large Language Models von Ahmad, Baleegh, Thakur, Shailja, Tan, Benjamin, Karri, Ramesh, Pearce, Hammond

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Make Every Move Count: LLM-based High-Quality RTL Code Generation Using MCTS von DeLorenzo, Matthew, Chowdhury, Animesh Basak, Gohil, Vasudev, Thakur, Shailja, Karri, Ramesh, Garg, Siddharth, Rajendran, Jeyavijayan

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AutoChip: Automating HDL Generation Using LLM Feedback von Thakur, Shailja, Blocklove, Jason, Pearce, Hammond, Tan, Benjamin, Garg, Siddharth, Karri, Ramesh

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CANOA: CAN Origin Authentication Through Power Side-Channel Monitoring von Thakur, Shailja, Moreno, Carlos, Fischmeister, Sebastian

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Towards the Imagenets of ML4EDA von Chowdhury, Animesh Basak, Thakur, Shailja, Pearce, Hammond, Karri, Ramesh, Garg, Siddharth

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Are Emily and Greg Still More Employable than Lakisha and Jamal? Investigating Algorithmic Hiring Bias in the Era of ChatGPT von Veldanda, Akshaj Kumar, Grob, Fabian, Thakur, Shailja, Pearce, Hammond, Tan, Benjamin, Karri, Ramesh, Garg, Siddharth

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(Security) Assertions by Large Language Models von Kande, Rahul, Hammond Pearce, Tan, Benjamin, Dolan-Gavitt, Brendan, Thakur, Shailja, Karri, Ramesh, Rajendran, Jeyavijayan

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VeriGen: A Large Language Model for Verilog Code Generation von Thakur, Shailja, Ahmad, Baleegh, Pearce, Hammond, Tan, Benjamin, Dolan-Gavitt, Brendan, Karri, Ramesh, Garg, Siddharth

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A generalizable saliency map-based interpretation of model outcome von Thakur, Shailja, Fischmeister, Sebastian

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Benchmarking Large Language Models for Automated Verilog RTL Code Generation von Thakur, Shailja, Ahmad, Baleegh, Fan, Zhenxing, Pearce, Hammond, Tan, Benjamin, Karri, Ramesh, Dolan-Gavitt, Brendan, Garg, Siddharth

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Can EDA Tool Feedback Improve Verilog Generation by LLMs? von Blocklove, Jason, Thakur, Shailja, Tan, Benjamin, Hammond Pearce, Garg, Siddharth, Karri, Ramesh

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