Superconductor digital electronics: Scalability and energy efficiency issues (Review Article) von Tolpygo, Sergey K.

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Very Large Scale Integration of Josephson-Junction-Based Superconductor Random Access Memories von Semenov, Vasili K., Polyakov, Yuri A., Tolpygo, Sergey K.

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Advanced Fabrication Processes for Superconductor Electronics: Current Status and New Developments von Tolpygo, Sergey K., Bolkhovsky, Vladimir, Rastogi, Ravi, Zarr, Scott, Day, Alexandra L., Golden, Evan, Weir, Terence J., Wynn, Alex, Johnson, Leonard M.

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Scalability of Superconductor Electronics: Limitations Imposed by AC Clock and Flux Bias Transformers von Tolpygo, Sergey K.

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Advanced Fabrication Processes for Superconducting Very Large-Scale Integrated Circuits von Tolpygo, Sergey K., Bolkhovsky, Vladimir, Weir, T. J., Wynn, Alex, Oates, D. E., Johnson, L. M., Gouker, M. A.

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Increasing integration scale of superconductor electronics beyond one million Josephson junctions von Tolpygo, Sergey K, Semenov, Vasili K

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Inductance of superconductor integrated circuit features with sizes down to 120 nm von Tolpygo, Sergey K, Golden, Evan B, Weir, Terence J, Bolkhovsky, Vladimir

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A New Family of bioSFQ Logic/Memory Cells von Semenov, Vasili K., Golden, Evan B., Tolpygo, Sergey K.

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BioSFQ Circuit Family for Neuromorphic Computing: Bridging Digital and Analog Domains of Superconductor Technologies von Semenov, Vasili K., Golden, Evan B., Tolpygo, Sergey K.

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Mutual and Self-Inductance in Planarized Multilayered Superconductor Integrated Circuits: Microstrips, Striplines, Bends, Meanders, Ground Plane Perforations von Tolpygo, Sergey K., Golden, Evan B., Weir, Terence J., Bolkhovsky, Vladimir

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Development of Self-Shunted Josephson Junctions For a Ten-Superconductor-Layer Fabrication Process: Nb/NbNx/Nb Junctions von Tolpygo, Sergey K., Rastogi, Ravi, Weir, Terence, Golden, Evan B., Bolkhovsky, Vladimir

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AC-Biased Shift Registers as Fabrication Process Benchmark Circuits and Flux Trapping Diagnostic Tool von Semenov, Vasili K., Polyakov, Yuri A., Tolpygo, Sergey K.

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SFQ Bias for SFQ Digital Circuits von Semenov, Vasili K., Golden, Evan B., Tolpygo, Sergey K.

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Self- and Mutual Inductance of NbN and Bilayer NbN/Nb Inductors in a Planarized Fabrication Process With Nb Ground Planes von Tolpygo, Sergey K., Golden, Evan B., Weir, Terence J., Bolkhovsky, Vladimir, Rastogi, Ravi

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Progress Toward Superconductor Electronics Fabrication Process With Planarized NbN and NbN/Nb Layers von Tolpygo, Sergey K., Mallek, Justin L., Bolkhovsky, Vladimir, Rastogi, Ravi, Golden, Evan B., Weir, Terence J., Johnson, Leonard M., Gouker, Mark A.

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Planarized Fabrication Process With Two Layers of SIS Josephson Junctions and Integration of SIS and SFS π-Junctions von Tolpygo, Sergey K., Bolkhovsky, Vladimir, Rastogi, Ravi, Zarr, Scott, Day, Alexandra L., Golden, Evan, Weir, Terence J., Wynn, Alex, Johnson, Leonard M.

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Wafer-Scale Characterization of a Superconductor Integrated Circuit Fabrication Process, Using a Cryogenic Wafer Prober von West, Joshua T., Kurlej, Arthur, Wynn, Alex, Rogers, Chad, Gouker, Mark A., Tolpygo, Sergey K.

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Inductance of Circuit Structures for MIT LL Superconductor Electronics Fabrication Process With 8 Niobium Layers von Tolpygo, Sergey K., Bolkhovsky, Vladimir, Weir, T. J., Galbraith, C. J., Johnson, Leonard M., Gouker, Mark A., Semenov, Vasili K.

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Deep sub-micron stud-via technology of superconductor VLSI circuits von Tolpygo, Sergey K, Bolkhovsky, V, Weir, T, Johnson, L M, Oliver, W D, Gouker, M A

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Reliability Studies of Nb/AlO x /Al/Nb Josephson Junctions Through Accelerated-Life Electrical Stress Testing von Goteti, Uday S., Denton, Matthew, Krause, Keith, Stephen, Andrew, Sellers, John A., Sullivan, Steffen, Hamilton, Michael C., Wynn, Alex, Tolpygo, Sergey K.

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