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  1. 1
    Latency-based instruction reservation in scheduler circuitry in processor

    Latency-based instruction reservation in scheduler circuitry in processor von SMITH, ROBERT, W, PULIYA DARSI SUSANA, TEKMON YVONNE CHARLOTTE

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  2. 2
    Minimum traversal of processor reorder buffers (ROB) for register rename mapping table (RMT) state recovery for interrupt instruction recovery in processor

    Minimum traversal of processor reorder buffers (ROB) for register rename mapping table (RMT) state recovery for interrupt instruction recovery in processor von SMITH, ROBERT, W, SEITH, KEVIN, R, PULIYA DARSI SUSANA, KOTHINTI NARESH VIGNYAN REDDY, TEKMON YVONNE CHARLOTTE

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  3. 3
    Enabling early execution of immediate move instructions with variable immediate value sizes in processor-based devices

    Enabling early execution of immediate move instructions with variable immediate value sizes in processor-based devices von PEREZ ARAM, SMITH, ROBERT, W, EL SHAKE RACHEL M, PULIYA DARSI SUSANA, KOTHINTI NARESH VIGNYAN REDDY, TEKMON YVONNE CHARLOTTE

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