Compute Solution for Tesla's Full Self-Driving Computer von Talpes, Emil, Sarma, Debjit Das, Venkataramanan, Ganesh, Bannon, Peter, McGee, Bill, Floering, Benjamin, Jalote, Ankit, Hsiong, Christopher, Arora, Sahil, Gorti, Atchyuth, Sachdev, Gagandeep S.

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The Microarchitecture of DOJO, Tesla's Exa-Scale Computer von Talpes, Emil, Sarma, Debjit Das, Williams, Doug, Arora, Sahil, Kunjan, Thomas, Floering, Benjamin, Jalote, Ankit, Hsiong, Christopher, Poorna, Chandrasekhar, Samant, Vaidehi, Sicilia, John, Nivarti, Anantha Kumar, Ramachandran, Raghuvir, Fischer, Tim, Herzberg, Ben, McGee, Bill, Venkataramanan, Ganesh, Banon, Pete

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Toward a multiple clock/voltage island design style for power-aware processors von Talpes, E., Marculescu, D.

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Energy awareness and uncertainty in microarchitecture-level design von Marculescu, D., Talpes, E.

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Increased Scalability and Power Efficiency by Using Multiple Speed Pipelines von Talpes, Emil, Marculescu, Diana

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SYSTEM AND METHOD FOR MATRIX MULTIPLICATION INSTRUCTION WITH FLOATING POINT OPERAND WITH A SPECIFIED BIAS von MCGEE, William, TALPES, Emil, DAS SARMA, Debjit

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Execution cache-based microarchitecture for power-efficient superscalar processors von Talpes, E., Marculescu, D.

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Variability and energy awareness: a microarchitecture-level perspective von Marculescu, Diana, Talpes, Emil

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SYSTEM AND METHOD FOR MATRIX MULTIPLICATION INSTRUCTION WITH FLOATING POINT OPERAND WITH A SPECIFIED BIAS von MCGEE, William, TALPES, Emil, DAS SARMA, Debjit

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SYSTEM AND METHOD FOR MATRIX MULTIPLICATION INSTRUCTION WITH FLOATING POINT OPERAND WITH A SPECIFIED BIAS von MCGEE, William, TALPES, Emil, DAS SARMA, Debjit

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COMPUTATIONAL ARRAY MICROPROCESSOR SYSTEM USING NON-CONSECUTIVE DATA FORMATTING von McGee, William, Talpes, Emil, Bannon, Peter Joseph

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Computational array microprocessor system using non-consecutive data formatting von McGee, William, Talpes, Emil, Bannon, Peter Joseph

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DATA PATH FOR SCALABLE MATRIX NODE ENGINE WITH MIXED DATA FORMATS von Das Sarma, Debjit, McGee, William, Talpes, Emil

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Vector computational unit von Das Sarma, Debjit, Talpes, Emil, Bannon, Peter Joseph

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INSTRUCTION SET ARCHITECTURE FOR A VECTOR COMPUTATIONAL UNIT von Das Sarma, Debjit, Talpes, Emil, Bannon, Peter Joseph

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Computational array microprocessor system with hardware arbiter managing memory requests von Hurd, Kevin Altair, Talpes, Emil, Bannon, Peter Joseph

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ACCELERATED MATHEMATICAL ENGINE von BANNON, Peter Joseph, HURD, Kevin Altair, TALPES, Emil

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VECTOR COMPUTATIONAL UNIT von BANNON, Peter Joseph, TALPES, Emil, DAS SARMA, Debjit

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SYSTEM AND METHOD FOR MATRIX MULTIPLICATION INSTRUCTION WITH FLOATING POINT OPERAND WITH A SPECIFIED BIAS von MCGEE, William, TALPES, Emil, DAS SARMA, Debjit

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Instruction set architecture for a vector computational unit von Das Sarma, Debjit, Talpes, Emil, Bannon, Peter Joseph

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