Highly Efficient Test Architecture for Low-Power AI Accelerators von Ibtesam, Muhammad, Solangi, Umair Saeed, Kim, Jinuk, Ansari, Muhammad Adil, Park, Sungju

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Time-Multiplexed 1687-Network for Test Cost Reduction von Ansari, Muhammad Adil, Jihun Jung, Dooyoung Kim, Sungju Park

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Dynamical Pseudo-Random Number Generator Using Reinforcement Learning von Park, Sungju, Kim, Kyungmin, Kim, Keunjin, Nam, Choonsung

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Fictional IR and imagination: Advancing narrative approaches von PARK-KANG, SUNGJU

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Test Architecture for Systolic Array of Edge-Based AI Accelerator von Solangi, Umair Saeed, Ibtesam, Muhammad, Ansari, Muhammad Adil, Kim, Jinuk, Park, Sungju

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An Improved LDPC ECC based on System Level Reprogramming for MLC NAND Flash von Kim, Jinuk, Jung, Jihun, Park, Sungju

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CAN-Based Aging Monitoring Technique for Automotive ASICs With Efficient Soft Error Resilience von Kim, Jinuk, Ibtesam, Muhammad, Kim, Dooyoung, Jung, Jihun, Park, Sungju

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Efficient Low-power Scan Test Method based on Exclusive Scan and Scan Chain Reordering von Kim, Dooyoung, Kim, Jinuk, Ibtesam, Muhammad, Solangi, Umair Saeed, Park, Sungju

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An Efficient SoC Test Technique by Reusing On/Off-Chip Bus Bridge von Jaehoon Song, Jaehoon Song, Hyunbean Yi, Hyunbean Yi, Juhee Han, Juhee Han, Sungju Park, Sungju Park

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On-Chip Support for NoC-Based SoC Debugging von Hyunbean Yi, Sungju Park, Kundu, Sandip

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Material Property-Estimate Technique Based on Natural Frequency for Updating Finite Element Model of Orthotropic Beams von Kim, Kookhyun, Park, Sungju, Lee, Sangjoong, Hwang, Seongjun, Kim, Sumin, Lee, Yonghee

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Time Division Multiplexing based Test Access for Stacked ICs von Ansari, Muhammad Adil, Solnagi, Umair Saeed, Kim, Jinuk, Bughio, Ahsin Murtaza, Park, Sungju

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Low-Cost Scan Test for IEEE-1500-Based SoC von Hyunbean Yi, Hyunbean Yi, Jaehoon Song, Jaehoon Song, Sungju Park, Sungju Park

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Growth factor-expressing human neural progenitor cell grafts protect motor neurons but do not ameliorate motor performance and survival in ALS mice von Park, Sungju, Kim, Hyoung-Tae, Yun, Seokhwan, Kim, Il-Sun, Lee, Jiyoon, Lee, Il-Shin, Park, Kook In

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Characterizing the Capacitive Crosstalk in SRAM Cells Using Negative Bit-Line Voltage Stress von Bae, Jongsun, Baeg, Sanghyeon, Park, Sungju

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Cost-efficient Chip Identification Method using Scan Flip-flop based Physically Unclonable Function von Kim, Dooyoung, Ansari, M. Adil, Jung, Jihun, Kim, Jinuk, Park, Sungju

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Low Power Scan Chain Reordering Method with Limited Routing Congestion for Code-based Test Data Compression von Kim, Dooyoung, Ansari, M. Adil, Jung, Jihun, Park, Sungju

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Efficient Pre-Bond Testing of TSV Defects Based on IEEE std. 1500 Wrapper Cells von Jung, Jihun, Ansari, Muhammad Adil, Kim, Dooyoung, Park, Sungju

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Hybrid Test Data Transportation Scheme for Advanced NoC-Based SoCs von Ansari, M. Adil, Kim, Dooyoung, Jung, Jihun, Park, Sungju

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A Scan Cell Design for Scan-Based Debugging of an SoC With Multiple Clock Domains von Hyunbean Yi, Kundu, Sandip, Sangwook Cho, Sungju Park

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