p/sup +/ polysilicon emitters for sub-0.5 mu m high-performance p-n-p von Warnock, J., Sun, J.Y.C., Bhattacharya, S.

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Current gain rolloff in graded-base SiGe heterojunction bipolar transistors von Crabbe, E.F., Cressler, J.D., Patton, G.L., Stork, J.M., Comfort, J.H., Sun, J.Y.-C.

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State-of-the-art RF/analog foundry technology von Lin, J.C.H., Yeh, T.H., Lee, C.Y., Chen, C.H., Tsay, J.L., Chen, S.H., Hsu, H.M., Chen, C.W., Huang, C.F., Chiang, J.M., Chang, A., Chang, R.Y., Chang, C.L., Wang, S.H., Wu, C.C., Lin, C.Y., Chu, Y.L., Chen, S.M., Hsu, C.K., Liou, R.S., Wong, S.C., Tang, D., Sun, J.Y.C.

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Technology and reliability challenges - a foundry perspective [semiconductor foundry] von Sun, J.Y.-C.

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IIIB-1 degradation of 77-K MOSFET characteristics due to channel hot electrons von Sun, J.Y.C., Wordeman, M.R.

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High-performance bipolar technology for improved ECL power delay von Warnock, J., Cressler, J.D., Jenkins, K.A., Stanis, C., Sun, J.Y.C., Tang, D.D., Petrillo, E., Hu, C.K.

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Mis-match characterization of 1.8 V and 3.3 V devices in 0.18 /spl mu/m mixed signal CMOS technology von Ta-Hsun Yeh, Lin, J.C.H., Shyh-Chyi Wong, Huang, H., Sun, J.Y.C.

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IIIB-2 Channel length characterization of LDD MOSFET's von Sun, J.Y.C., Wordeman, M.R., Laux, S.E.

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A high performance BiCMOS technology using 0.25 mu m CMOS and double poly 47 GHz bipolar von Shahidi, G.G., Warnock, J., Davari, B., Wu, B., Taur, Y., Wong, C., Chen, C.L., Rodriguez, M., Tang, D.D., Jenkins, K., McFarland, P.A., Schulz, R., Zicherman, D., Coane, P., Klaus, D., Sun, J.Y.C., Polcari, M., Ning, T.H.

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Using erase self-detrapped effect to eliminate the flash cell program/erase cycling V/sub th/ window close von Lee, J.H., Peng, K.R., Shih, J.R., Chen, S.H., Yeh, J.K., Su, H.D., Ho, M.C., Kuo, D.S., Liew, B.K., Sun, J.Y.C.

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Scaling variance, invariance and prediction of design rule: from 0.25-/spl mu/m to 0.10-/spl mu/m nodes in the era of foundry manufacturing von Doong, K.Y.-Y., Ting, J.K., Sunnys Hsieh, Lin, S.C., Binson Shen, Guo, J.C., Young, K.L., Chen, I.C., Sun, J.Y.C., Wang, J.K.

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Application-dependent scaling tradeoffs and optimization in the SoC era von Diaz, C.H., Mi-Chang Chang, Ong, T.C., Sun, J.Y.C.

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An investigation of the RF/analog characteristics of multiple variants SiGe HBTs for optical and wireless applications von Yang, M.T., Kuo, D.C.W., Ho, P.P.C., Kuo, C.W., Yeh, T.J., Chang, A.K.L., Lee, C.Y., Chia, Y.T., Chern, G.J., Young, K.L., Tang, D.D., Sun, J.Y.C.

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Foundry technology for the next decade von Sun, J.Y.C., Shang-Yi Chiang, Liu, M.

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A low-power static frequency divider circuit in bipolar technology von Toh, K.Y., Tzeng, Y.C., Warnock, J.D., Petrillo, E.J., Chuang, K.C.T., Sun, J.Y.C.

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Ultra-low leakage 0.16 /spl mu/m CMOS for low-standby power applications von Wu, C.C., Diaz, C.H., Lin, B.L., Chang, S.Z., Wang, C.C., Liaw, J.J., Wang, C.H., Young, K.K., Lee, K.H., Liew, B.K., Sun, J.Y.C.

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A 90 nm CMOS MS/RF based foundry SOC technology comprising superb 185 GHz f/sub T/ RFMOS and versatile, high-Q passive components for cost/performance optimization von Chen, C.H., Chang, C.S., Chao, C.P., Kuan, J.F., Chang, C.L., Wang, S.H., Hsu, H.M., Lien, W.Y., Tsai, Y.C., Lin, H.C., Wu, C.C., Huang, C.F., Chen, S.M., Tseng, P.M., Chen, C.W., Ku, C.C., Lin, T.Y., Chang, C.F., Lin, H.J., Tsai, M.R., Chen, S., Chen, C.F., Wei, M.Y., Wang, Y.J., Lin, J.C.H., Chen, W.M., Chang, C.C., King, M.C., Huang, C.M., Lin, C.T., Guo, J.C., Chern, G.J., Tang, D.D., Sun, J.Y.C.

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A 0.13 /spl mu/m CMOS technology with 193 nm lithography and Cu/low-k for high performance applications von Young, K.K., Wu, S.Y., Wu, C.C., Wang, C.H., Lin, C.T., Cheng, J.Y., Chiang, M., Chen, S.H., Lo, T.C., Chen, Y.S., Chen, J.H., Chen, L.J., Hou, S.Y., Law, J.J., Chang, T.E., Hou, C.S., Shih, J., Jeng, S.M., Hsieh, H.C., Ku, Y., Yen, T., Tao, H., Chao, L.C., Shue, S., Jang, S.M., Ong, T.C., Yu, C.H., Liang, M.S., Diaz, C.H., Sun, J.Y.C.

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A 0.18 /spl mu/m CMOS logic technology with dual gate oxide and low-k interconnect for high-performance and low-power applications von Diaz, C.H., Young, K.L., Hsu, J.H., Lin, J.C.H., Hou, C.S., Lin, C.T., Liaw, J.J., Wu, C.C., Su, C.W., Wang, C.H., Ting, J.K., Yang, S.S., Lee, K.Y., Wu, S.Y., Tsai, C.C., Tao, H.J., Jang, S.M., Shue, S.L., Hsieh, H.C., Wang, Y.Y., Chen, C.C., Yang, S.C., Fu, S., Chang, S.Z., Lo, T.C., Wu, J.Y., Shy, J.S., Liu, C.W., Chen, S.H., Lin, B.L., Liew, B.K., Yen, T., Yu, C.H., Chao, Y.C., Liang, M.S., Wang, C., Sun, J.Y.C.

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A highly manufacturable 0.25 /spl mu/m multiple-Vt dual gate oxide CMOS process for logic/embedded IC foundry technology von Chang, M.H., Ting, J.K., Shy, J.S., Chen, L., Liu, C.W., Wu, J.Y., Pan, K.H., Hou, C.S., Tu, C.C., Chen, Y.H., Sue, S.L., Jang, S.M., Yang, S.C., Tsai, C.S., Chen, C.H., Tao, H.J., Tsai, C.C., Hsieh, H.C., Wang, Y.Y., Chang, R.Y., Cheng, K.B., Chu, T.Y., Yen, T.N., Wang, P.S., Weng, J.W., Hsu, J.H., Ho, Y.S., Ho, C.H., Huang, Y.C., Shiue, R.Y., Liew, B.K., Yu, C.H., Sun, S.C., Sun, J.Y.C.

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