A Multi-Path Gated Ring Oscillator TDC With First-Order Noise Shaping von Straayer, M.Z., Perrott, M.H.

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A Highly Digital MDLL-Based Clock Multiplier That Leverages a Self-Scrambling Time-to-Digital Converter to Achieve Subpicosecond Jitter Performance von Helal, B.M., Straayer, M.Z., Gu-Yeon Wei, Perrott, M.H.

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A 12-Bit, 10-MHz Bandwidth, Continuous-Time [Formula Omitted] ADC With a 5-Bit, 950-MS/s VCO-Based Quantizer von Straayer, M Z, Perrott, M H

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A Low-Noise Wide-BW 3.6-GHz Digital [Formula Omitted] Fractional-N Frequency Synthesizer With a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation von Hsu, Chun-Ming, Straayer, M Z, Perrott, M H

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A 12b 200MS/s frequency scalable zero-crossing based pipelined ADC in 55nm CMOS von Soon-Kyun Shin, Rudell, J. C., Daly, D. C., Munoz, C. E., Dong-Young Chang, Gulati, K., Hae-Seung Lee, Straayer, M. Z.

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Cognitive underpinnings of beliefs and confidence in beliefs about fully automated vehicles von Sanbonmatsu, David M., Strayer, David L., Yu, Zhenghui, Biondi, Francesco, Cooper, Joel M.

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A Low Jitter 1.6 GHz Multiplying DLL Utilizing a Scrambling Time-to-Digital Converter and Digital Correlation von Helal, B.M., Straayer, M.Z., Gu-Yeon Wei, Perrott, M.H.

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