A 440-ps 64-bit adder in 1.5-V/0.18-[micro]m partially depleted SOI technology von Stasiak, D.L, Mounes-Toussi, F, Storino, S.N

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A 0.2-μm, 1.8-V, SOI, 550-MHZ, 64-b PowerPC microprocessor with copper interconnects von Aipperspach, A.G., Allen, D.H., Cox, D.T., Phan, N.V., Storino, S.N.

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A double-precision multiplier with fine-grained clock-gating support for a first-generation CELL processor von Kuang, J.B., Buchholtz, T.C., Dance, S.M., Warnock, J.D., Storino, S.N., Wendel, D., Bradley, D.H.

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The design and implementation of double-precision multiplier in a first-generation CELL processor von Kuang, J.B., Buchholtz, T.C., Dance, S.M., Warnock, J.D., Storino, S.N., Wendel, D., Bradley, D.H.

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A 0.2 /spl mu/m 1.8 V SOI 550 MHz 64 b PowerPC microprocesser with copper interconnects von Allen, D.H., Aipperspach, A.G., Cox, D.T., Phan, N.V., Storino, S.N.

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Methods and appts for bipolar elimination in silcon-on-insulator (sol) domino circuits von J.V. TRAN, S.N. STORINO, A.D. DAVIES

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