A scalable single-chip multi-processor architecture with on-chip RTOS kernel von Theelen, B.D., Verschueren, A.C., Reyes Suárez, V.V., Stevens, M.P.J., Nuñez, A.

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Object oriented system analysis for VLSI von Hu, Yun-Chao, Verschueren, Ad, Stevens, M.P.J.

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System level models for real-time communication von van der Putten, P.H.A., Voeten, J.P.M., Geilen, M.C.W., Stevens, M.P.J.

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Behaviour-preserving transformations in SHE: a formal approach to architecture design von Voeten, J.P.M., van der Putten, P.H.A., Stevens, M.P.J.

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System level modelling for hardware/software systems von Voeten, J.P.M., van der Putten, P.H.A., Geilen, M.C.W., Stevens, M.P.J.

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System-level testability of hardware/software systems von Vranken, H.P.E., Stevens, M.P.J., Segers, M.T.M., van Rhee, J.H.M.M.

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Analysis of a protocol handling system specification and its performance von Benders, L.P.M., van den Hoorn, H.M., Stevens, M.P.J.

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Systematic development of industrial control systems using software/hardware engineering von Voeten, J.P.M., van der Putten, P.H.A., Stevens, M.P.J.

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Petri net modelling in embedded system design von Benders, L.P.M., Stevens, M.P.J.

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Object-oriented modelling and specification using SHE von Geilen, M.C.W., Voeten, J.P.M., van der Putten, P.H.A., van Bokhoven, L.J., Stevens, M.P.J.

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Design-for-debug in hardware/software co-design von Vranken, H.P.E., Stevens, M.P.J., Segers, M.T.M.

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System level design methodology von van der Putten, P.H.A., Voeten, J.P.M., Geilen, M.C.W., Stevens, M.P.J.

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TL: A system specification system von Benders, L.P.M., Stevens, M.P.J.

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System level VLSI design von Stevens, M.P.J., Budzelaar, F.P.M.

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Task level behavioral hardware description von Benders, L.P.M., Stevens, M.P.J.

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The design of a real-time communication network for parallel processing von Johann, C.F.M., Loonen, R., Stevens, M.P.J.

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Task level specification and communication von Benders, L.P.M., Stevens, M.P.J.

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Compilation techniques for a high level language processor von Watson, B.W., Withagen, W.J., Stevens, M.P.J.

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Pipelining a memory based CISC processor von Smeets, J.P.C.F.H., Withagen, W.J., Stevens, M.P.J.

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A universal traffic controller based on a microprocessor von Stevens, M.P.J, Segers, M.T.M, Alma, J.G.H

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