Thermal-Aware Scheduling for Future Chip Multiprocessors von Stavrou, Kyriakos, Trancoso, Pedro

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Hardware Budget and Runtime System for Data-Driven Multithreaded Chip Multiprocessor von Stavrou, Kyriakos, Trancoso, Pedro, Evripidou, Paraskevas

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TSIC: Thermal Scheduling Simulator for Chip Multiprocessors von Stavrou, Kyriakos, Trancoso, Pedro

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Thermal-Aware Scheduling for Future Chip Multiprocessors von Stavrou, Kyriakos, Trancoso, Pedro

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DDM-CMP: Data-Driven Multithreading on a Chip Multiprocessor von Stavrou, Kyriakos, Evripidou, Paraskevas, Trancoso, Pedro

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HelperCore_DB:Exploiting Multicore Technology for Databases von Papadopoulos, Kostas, Stavrou, Kyriakos, Trancoso, Pedro

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A Case for Chip Multiprocessors Based on the Data-Driven Multithreading Model von Trancoso, Pedro, Evripidou, Paraskevas, Stavrou, Kyriakos, Kyriacou, Costas

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Quantitative characterization of the software layer of a HW/SW co-designed processor von Cano Reyes, José, Kumar, Rakesh, Brankovic, Aleksandar, Pavlou, Demos, Stavrou, Kyriakos, Gibert Codina, Enric, Martínez, Alejandro, González Colás, Antonio María

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HW/SW co-designed processors: Challenges, design choices and a simulation infrastructure for evaluation von Kumar, Rakesh, Cano, José, Brankovic, Aleksandar, Pavlou, Demos, Stavrou, Kyriakos, Gibert Codina, Enric, Martínez, Alejandro, González Colás, Antonio María

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Performance analysis and predictability of the software layer in Dynamic Binary Translators/Optimizers von Brankovic, Aleksandar, Stavrou, K, Gibert Codina, Enric, Gonzalez, Antonio

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Speculative hardware/software co-designed floating-point multiply-add fusion von Lupon, Marc, Gibert, Enric, Magklis, Grigorios, Samudrala, Sridhar, Martínez, Raúl, Stavrou, Kyriakos, Ditzel, David R.

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Speculative hardware/software co-designed floating-point multiply-add fusion von Lupon, Marc, Gibert, Enric, Magklis, Grigorios, Samudrala, Sridhar, Martínez, Raúl, Stavrou, Kyriakos, Ditzel, David R.

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Warm-up simulation methodology for HW/SW co-designed processors von Brankovic, Aleksandar, Stavrou, K, Gibert Codina, Enric, González Colás, Antonio María

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Partial commits in dynamic binary translation based systems von LUPON MARC, STAVROU KYRIAKOS A, MARTINEZ RAUL, CODINA ENRIC GIBERT

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Accurate off-line phase classification for HW/SW co-designed processors von Brankovic, Aleksandar, Stavrou, Kyriakos, Gibert Codina, Enric, González Colás, Antonio María

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Thermal-Aware Scheduling: A Solution for Future Chip Multiprocessors Thermal Problems von Stavrou, K., Trancoso, P.

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PARTIAL COMMITS IN DYNAMIC BINARY TRANSLATION BASED SYSTEMS von LUPON MARC, STAVROU KYRIAKOS A, MARTINEZ RAUL, CODINA ENRIC GIBERT

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Combined floating point multiplier adder with intermediate rounding logic von LUPON MARC, STAVROU KYRIAKOS A, SAMUDRALA SRIDHAR, MARTINEZ RAUL, CODINA ENRIC GIBERT, MAGKLIS GRIGORIOS

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Mechanism for facilitating dynamic and efficient fusion of computing instructions in software programs von LUPON MARC, STAVROU KYRIAKOS A, SAMUDRALA SRIDHAR, MARTINEZ RAUL, CODINA ENRIC GIBERT, MAGKLIS GRIGORIOS

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Split-word memory von BRETSCHNEIDER BERT, STAVROU KYRIAKOS A, BORKOWSKI AXEL, NAETHKE LUTZ, THEUER RAINER

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