Introduction to the Special Section on the 2019 IEEE International Solid-State Circuits Conference (ISSCC) von Mohseni, Pedram, Vangal, Sriram R.

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An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS von Vangal, S.R., Howard, J., Ruhl, G., Dighe, S., Wilson, H., Tschanz, J., Finan, D., Singh, A., Jacob, T., Jain, S., Erraguntla, V., Roberts, C., Hoskote, Y., Borkar, N., Borkar, S.

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A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling von Howard, J, Dighe, S, Vangal, S R, Ruhl, G, Borkar, N, Jain, S, Erraguntla, V, Konow, M, Riepen, M, Gries, M, Droege, G, Lund-Larsen, T, Steibl, S, Borkar, S, De, V K, Van Der Wijngaart, R

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Wide-Range Many-Core SoC Design in Scaled CMOS: Challenges and Opportunities von Vangal, Sriram, Paul, Somnath, Hsu, Steven, Agarwal, Amit, Kumar, Saurabh, Krishnamurthy, Ram, Krishnamurthy, Harish, Tschanz, James, De, Vivek, Kim, Chris H.

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An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS von Vangal, Sriram, Howard, Jason, Ruhl, Gregory, Dighe, Saurabh, Wilson, Howard, Tschanz, James, Finan, David, Iyer, Priya, Singh, Arvind, Jacob, Tiju, Jain, Shailendra, Venkataraman, Sriram, Hoskote, Yatin, Borkar, Nitin

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Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor von Dighe, S, Vangal, S R, Aseron, P, Kumar, S, Jacob, T, Bowman, K A, Howard, J, Tschanz, J, Erraguntla, V, Borkar, N, De, V K, Borkar, S

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A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS von Jain, S., Khare, S., Yada, S., Ambili, V., Salihundam, P., Ramani, S., Muthukumar, S., Srinivasan, M., Kumar, A., Gb, S. K., Ramanarayanan, R., Erraguntla, V., Howard, J., Vangal, S., Dighe, S., Ruhl, G., Aseron, P., Wilson, H., Borkar, N., De, V., Borkar, S.

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A Sub-cm3 Energy-Harvesting Stacked Wireless Sensor Node Featuring a Near-Threshold Voltage IA-32 Microcontroller in 14-nm Tri-Gate CMOS for Always-ON Always-Sensing Applications von Paul, Somnath, Honkote, Vinayak, Kim, Ryan Gary, Majumder, Turbo, Aseron, Paolo A., Grossnickle, Vaughn, Sankman, Robert, Mallik, Debendra, Tao Wang, Vangal, Sriram, Tschanz, James W., De, Vivek

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Near-Threshold Voltage Design Techniques for Heterogenous Manycore System-on-Chips von Vangal, Sriram, Paul, Somnath, Hsu, Steven, Agarwal, Amit, Krishnamurthy, Ram, Tschanz, James, De, Vivek

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An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and } Optimization von Meinerzhagen, Pascal A., Tokunaga, Carlos, Malavasi, Andres, Vaidya, Vaibhav, Mendon, Ashwin, Mathaikutty, D., Kulkarni, Jaydeep, Augustine, Charles, Cho, Minki, Kim, Stephen T., Matthew, George E., Jain, Rinkle, Ryan, Joseph, Peng, Chung-Ching, Paul, Somnath, Vangal, Sriram, Perez Esparza, Brando, Cuellar, L., Woodman, M., Iyer, Bala, Maiyuran, Subramaniam, Chinya, G., Zou, Xiang, Liao, Yuyun, Ravichandran, Krishnan, Wang, H., Khellah, Muhammad M., Tschanz, James W., De, Vivek

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IA-32 Processor with a Wide-Voltage-Operating Range in 32-nm CMOS von Ruhl, G., Dighe, S., Jain, S., Khare, S., Vangal, S. R.

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A 6.2-GFlops Floating-Point Multiply-Accumulator With Conditional Normalization von Vangal, S.R., Hoskote, Y.V., Borkar, N.Y., Alvandpour, A.

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A 5-GHz Mesh Interconnect for a Teraflops Processor von Hoskote, Y., Vangal, S., Singh, A., Borkar, N., Borkar, S.

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A TCP offload accelerator for 10 Gb/s Ethernet in 90-nm CMOS von Hoskote, Y., Bloechel, B.A., Dermer, G.E., Erraguntla, V., Finan, D., Howard, J., Klowden, D., Narendra, S.G., Ruhl, G., Tschanz, J.W., Sriram Vangal, Veeramachaneni, V., Wilson, H., Jianping Xu, Borkar, N.

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A 2 Tb/s 6 × 4 Mesh Network for a Single-Chip Cloud Computer With DVFS in 45 nm CMOS von SALIHUNDAM, Praveen, JAIN, Shailendra, JACOB, Tiju, KUMAR, Shasi, ERRAGUNTLA, Vasantha, HOSKOTE, Yatin, VANGAL, Sriram, RUHL, Gregory, BORKAR, Nitin

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A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS von Howard, J., Dighe, S., Hoskote, Y., Vangal, S., Finan, D., Ruhl, G., Jenkins, D., Wilson, H., Borkar, N., Schrom, G., Pailet, F., Jain, S., Jacob, T., Yada, S., Marella, S., Salihundam, P., Erraguntla, V., Konow, M., Riepen, M., Droege, G., Lindemann, J., Gries, M., Apel, T., Henriss, K., Lund-Larsen, T., Steibl, S., Borkar, S., De, V., Van Der Wijngaart, R., Mattson, T.

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A Sub-cm 3 Energy-Harvesting Stacked Wireless Sensor Node Featuring a Near-Threshold Voltage IA-32 Microcontroller in 14-nm Tri-Gate CMOS for Always-ON Always-Sensing Applications von Paul, Somnath, Honkote, Vinayak, Kim, Ryan Gary, Majumder, Turbo, Aseron, Paolo A., Grossnickle, Vaughn, Sankman, Robert, Mallik, Debendra, Wang, Tao, Vangal, Sriram, Tschanz, James W., De, Vivek

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Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging von Tschanz, James, Kim, Nam Sung, Dighe, Saurabh, Howard, Jason, Ruhl, Gregory, Vangal, Sriram, Narendra, Siva, Hoskote, Yatin, Wilson, Howard, Lam, Carol, Shuman, Matthew, Tokunaga, Carlos, Somasekhar, Dinesh, Tang, Stephen, Finan, David, Karnik, Tanay, Borkar, Nitin, Kurd, Nasser, De, Vivek

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Performance and Energy Efficient Building Blocks for Network-on-Chip Architectures von Vangal, Sriram R.

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Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor von Dighe, S., Vangal, S., Aseron, P., Kumar, S., Jacob, T., Bowman, K., Howard, J., Tschanz, J., Erraguntla, V., Borkar, N., De, V., Borkar, S.

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