Molecular Caches: A caching structure for dynamic creation of application-specific Heterogeneous cache regions von Varadarajan, Keshavan, Nandy, S. K., Sharda, Vishal, Bharadwaj, Amrutur, Iyer, Ravi, Makineni, Srihari, Newell, Donald

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Exploring Large-Scale CMP Architectures Using ManySim von Zhao, Li, Iyer, Ravi, Moses, Jaideep, Illikkal, Ramesh, Makineni, Srihari, Newell, Don

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QoS policies and architecture for cache/memory in CMP platforms von Iyer, Ravi, Zhao, Li, Guo, Fei, Illikkal, Ramesh, Makineni, Srihari, Newell, Don, Solihin, Yan, Hsu, Lisa, Reinhardt, Steve

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CHOP: Adaptive filter-based DRAM caching for CMP server platforms von Xiaowei Jiang, Madan, Niti, Li Zhao, Upton, Mike, Iyer, Ravishankar, Makineni, Srihari, Newell, Donald, Solihin, Yan, Balasubramonian, Rajeev

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TCP onloading for data center servers von Regnier, G., Makineni, S., Illikkal, I., Iyer, R., Minturn, D., Huggahalli, R., Newell, D., Cline, L., Foong, A.

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CHOP: Integrating DRAM Caches for CMP Server Platforms von Xiaowei Jiang, Madan, Niti, Li Zhao, Upton, Mike, Iyer, Ravi, Makineni, Srihari, Newell, Don, Solihin, Yan, Balasubramonian, Rajeev

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Characterization of network processing overheads in Xen von Apparao, P., Makineni, S., Newell, D.

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Characterization of Direct Cache Access on multi-core systems and 10GbE von Kumar, A., Huggahalli, R., Makineni, S.

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Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy von Madan, N., Li Zhao, Muralimanohar, N., Udipi, A., Balasubramonian, R., Iyer, R., Makineni, S., Newell, D.

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Hardware Support for Accelerating Data Movement in Server Platform von Li Zhao, Bhuyan, L.N., Iyer, R., Makineni, S., Newell, D.

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ACCESS: Smart scheduling for asymmetric cache CMPs von Xiaowei Jiang, Mishra, A, Li Zhao, Iyer, R, Zhen Fang, Srinivasan, S, Makineni, S, Brett, P, Das, C R

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Architectural characterization of TCP/IP packet processing on the Pentium/spl reg/ M microprocessor von Srihari Makineni, Ravi Iyer

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Re-examining cache replacement policies von Zebchuk, J., Makineni, S., Newell, D.

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QoS policies and architecture for cache/memory in CMP platforms von Iyer, Ravi, Zhao, Li, Guo, Fei, Illikkal, Ramesh, Srihari, Makineni, Newell, Don, Solihin, Yan, Hsu, Lisa, Reinhardt, Steve

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Evaluating implications of Virtual Worlds on server architecture using Second Life von Makineni, S., Tickoo, O., Terrell, A., Young, J., Newell, D.

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Boomerang: Reducing Power Consumption of Response Packets in NoCs with Minimal Performance Impact von Zhen Fang, Hallnor, Erik G, Bin Li, Leddige, Michael, Donglai Dai, Seung Eun Lee, Makineni, Srihari, Iyer, Ravi

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Achieving 10Gbps network processing: are we there yet? von Govindarajan, Priya, Makineni, Srihari, Newell, Donald, Iyer, Ravi, Huggahalli, Ram, Kumar, Amit

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FREQUENCY SCALING FOR PER-CORE ACCELERATOR ASSIGNMENTS von PURANDARE, Adwait, ELSAYED, Rany T, MUKHERJEE, Udayan, MOSUR, Lokpraveen, CHANDWANI, Neelam, PALERMO, Stephen T, MAKINENI, Srihari, BOMMALINGAIAHNAPALLYA, Shubha

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To Snoop or Not to Snoop: Evaluation of Fine-Grain and Coarse-Grain Snoop Filtering Techniques von Young, Jessica, Makineni, Srihari, Iyer, Ravishankar, Newell, Don, Moga, Adrian

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SYSTEMS, METHODS, AND APPARATUS FOR WORKLOAD OPTIMIZED CENTRAL PROCESSING UNITS (CPUS) von PALERMO, Stephen, GADIYAR, Rajesh, QURESHI, Uzair, MOSUR, Lokpraveen, SHAH, Pinkesh, ELSAYED, Rany, CHANDWANI, Neelam, SHAH, Shrikant, MAKINENI, Srihari, BOMMALINGAIAHNAPALLYA, Shubha

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