Increasing the Applicability of Scalar Replacement von So, Byoungro, Hall, Mary

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Intel's Array Building Blocks: A retargetable, dynamic compiler and embedded language von Newburn, C J, Byoungro So, Zhenying Liu, McCool, M, Ghuloum, A, Toit, S D, Zhi Gang Wang, Zhao Hui Du, Yongjian Chen, Gansha Wu, Peng Guo, Zhanglin Liu, Dan Zhang

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Evaluating automatic parallelization in SUIF von Sungdo Moon, Byoungro So, Hall, M.W.

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A Case for Combining Compile-Time and Run-Time Parallelization von Moon, Sungdo, So, Byoungro, Hall, Mary W., Murphy, Brian

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Combining Compile‐Time and Run‐Time Parallelization von Moon, Sungdo, So, Byoungro, Hall, Mary W.

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Optimizing Compiler for the CELL Processor von Eichenbergert, Alexandre E., O'Brien, Kathryn, O'Brien, Kevin, Wu, Peng, Chen, Tong, Oden, Peter H., Prener, Daniel A., Shepherd, Janice C., So, Byoungro, Sura, Zehra, Wang, Amy, Zhang, Tao, Zhao, Peng, Gschwind, Michael

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Coarse-grain pipelining on multiple FPGA architectures von Ziegler, H., Byoungro So, Hall, M., Diniz, P.C.

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Automatic mapping of C to FPGAs with the DEFACTO compilation and synthesis system von Diniz, Pedro, Hall, Mary, Park, Joonseok, So, Byoungro, Ziegler, Heidi

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Custom Data Layout for Memory Parallelism von So, Byoungro, Hall, Mary W., Ziegler, Heidi E.

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Bridging the Gap between Compilation and Synthesis in the DEFACTO System von Diniz, Pedro, Hall, Mary, Park, Joonseok, So, Byoungro, Ziegler, Heidi

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Search Space Properties for Mapping Coarse-Grain Pipelined FPGA Applications von Ziegler, Heidi, Hall, Mary, So, Byoungro

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Methods and apparatus to optimize the parallel execution of software processes von So, Byoungro, Ghuloum, Anwar M, Wu, Youfeng

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A compiler approach to fast hardware design space exploration in FPGA-based systems von So, Byoungro, Hall, Mary W., Diniz, Pedro C.

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Compiler implemented software cache in which non-aliased explicitly fetched data are excluded von Chen, Tong, O'Brien, John Kevin Patrick, O'Brien, Kathryn, So, Byoungro, Sura, Zehra N, Zhang, Tao

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Intel's Array Building Blocks: A retargetable, dynamic compiler and embedded language von Newburn, Chris J., So, Byoungro, Liu, Zhenying, McCool, Michael, Ghuloum, Anwar, Toit, Stefanus Du, Wang, Zhi Gang, Du, Zhao Hui, Chen, Yongjian, Wu, Gansha, Guo, Peng, Liu, Zhanglin, Zhang, Dan

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Compiler implemented software cache method in which non-aliased explicitly fetched data are excluded von Chen, Tong, O'Brien, John Kevin Patrick, O'Brien, Kathryn, So, Byoungro, Sura, Zehra N, Zhang, Tao

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A compiler approach to fast hardware design space exploration in FPGA-based systems von So, Byoungro, Hall, Mary W, Diniz, Pedro C

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Methods and apparatus to optimize the parallel execution of software processes von GHULOUM ANWAR M, WU YOUFENG, SO BYOUNGRO

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Compiler implemented software cache in which non-aliased explicitly fetched data are excluded von SURA ZEHRA N, O'BRIEN JOHN KEVIN PATRICK, ZHANG TAO, SO BYOUNGRO, CHEN TONG, O'BRIEN KATHRYN

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Compiler implemented software cache method in which non-aliased explicitly fetched data are excluded von SURA ZEHRA N, O'BRIEN JOHN KEVIN PATRICK, ZHANG TAO, SO BYOUNGRO, CHEN TONG, O'BRIEN KATHRYN

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