Treffer 1 - 7 von 7 für Suche 'Sivaswamy, Satish B', Suchdauer: 0,47s Treffer weiter einschränken
  1. 1
    DEADLOCK DETECTION AND PREVENTION FOR ROUTING PACKET-SWITCHED NETS IN ELECTRONIC SYSTEMS

    DEADLOCK DETECTION AND PREVENTION FOR ROUTING PACKET-SWITCHED NETS IN ELECTRONIC SYSTEMS von Deshmukh, Nitin, Sivaswamy, Satish B, Venkatakrishnan, Sreesan

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  2. 2
    Application implementation and buffer allocation for a data processing engine array

    Application implementation and buffer allocation for a data processing engine array von Deshmukh, Nitin, Sivaswamy, Satish B, Guttag, Brian

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  3. 3
    APPLICATION IMPLEMENTATION AND BUFFER ALLOCATION FOR A DATA PROCESSING ENGINE ARRAY

    APPLICATION IMPLEMENTATION AND BUFFER ALLOCATION FOR A DATA PROCESSING ENGINE ARRAY von Deshmukh, Nitin, Sivaswamy, Satish B, Guttag, Brian

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  4. 4
    Fixing hold time violations using hold time budgets and slacks of setup times

    Fixing hold time violations using hold time budgets and slacks of setup times von Sivaswamy, Satish B, Kannan, Parivallal

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  5. 5
    Partition wire assignment for routing multi-partition circuit designs

    Partition wire assignment for routing multi-partition circuit designs von Deshmukh, Nitin, Sivaswamy, Satish B, Gasparyan, Grigor S, Mkrtchyan, Garik

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  6. 6
    Synchronous clock domain crossing skew optimization and multi-clock buffer (MBUFG)

    Synchronous clock domain crossing skew optimization and multi-clock buffer (MBUFG) von Satter, Thomas O, Eslami Dehkordi, Mehrdad, Mezei, Nicholas A, Sivaswamy, Satish B, Zhang, Chun, Mkrtchyan, Garik, Revenu, Frederic, Mueller, Frank

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  7. 7
    Representation of complex timing characteristics of startpoint-endpoint pairs in a circuit design

    Representation of complex timing characteristics of startpoint-endpoint pairs in a circuit design von Srinivasan Atul, Manaker, Jr. Walter A, Sivaswamy Satish B, Zejda Jindrich, Ganusov Ilya K, Devlin Benjamin S

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