A Reed-Solomon product-code (RS-PC) decoder chip for DVD applications von Hsie-Chia Chang, Shung, C.B., Chen-Yi Lee

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Two systolic architectures for modular multiplication von Wei-Chang Tsai, Shung, C.B., Sheng-Jyh Wang

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A 4-Gbps Uncompressed Wireless HD A/V Transceiver Chipset von Gilbert, J.M., Doan, C.H., Emami, S., Shung, C.B.

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X-Ray- and Ultraviolet-Radiation-Induced Mutations in Muta™ Mouse von Ono, Tetsuya, Ikehata, Hironobu, Hosoi, Yoshio, Shung, Bok-Shil, Kurishita, Akihiro, Wang, Xue, Yamamoto, Kazuo, Suzuki, Takayoshi, Sofuni, Toshio

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Geometry for trochoidal-type machines with conjugate envelopes von Shung, J.B, Pennock, G.R

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Impact of Location of Epicardial Adipose Tissue, Measured by Coronary Artery Calcium-Scoring Computed Tomography on Obstructive Coronary Artery Disease von Wu, Fu-Zong, MD, Huang, Yi-Luan, MD, Wang, Yen-Chi, MD, Lin, Huey-Shyan, PhD, Chen, Chien-Shung, BS, Ju, Yu-Jen, MS, Chiou, Kuan-Rau, MD, Cheng, Chin-Chang, MD, Wu, Ming-Ting, MD

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New serial architecture for the Berlekamp-Massey algorithm von Hsie-Chia Chang, Shung, C.B.

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The direct contact problem in a trochoidal-type machine von Shung, J.B., Pennock, G.R.

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An integrated CAD system for algorithm-specific IC design von Shung, C.B., Jain, R., Rimey, K., Wang, E., Srivastava, M.B., Richards, B.C., Lettang, E., Khalid Azim, S., Thon, L., Hilfinger, P.N., Rabaey, J.M., Brodersen, R.W.

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Real-time recording results for a trellis-coded partial response (TCPR) system von Thapar, H.K., Shung, C.B., Rae, J.W., Karabed, R., Siegel, P.H.

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A 30-MHz trellis codec chip for partial-response channels von Shung, C.B., Siegel, P.H., Thapar, H.K., Karabed, R.

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Design and implementation of a low-level image segmentation architecture ― LISA von BLANZ, W. E, SHUNG, C. B, COX, C. E, GREINER, W, DOM, B. E, PEKOVIC, D

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Guest editorial - Topics in circuits for communications series: analog and digital circuits for wireless communications von Shung, B.

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Area-efficient architectures for the Viterbi algorithm II. Applications von Shung, C.B., Lin, H.-D., Cypher, R., Siegel, P.H., Thapar, H.K.

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Area-efficient architectures for the Viterbi algorithm. I. Theory von Shung, C.B., Lin, H.-D., Cypher, R., Siegel, P.H., Thapar, H.K.

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A packet-memory-integrated 44 Gb/s switching processor with a 10 Gb port and 12 Gb ports von Lau, M., Shieh, S., Pei-Feng Wang, Smith, B., Min-Shueh Yuan, Lee, D., Gaba, J., Chao, J., Shung, B., Cheng-Chung Shih

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Induction of c-fos gene expression by exposure to a static magnetic field in HeLaS3 cells von HIRAOKA, M, MIYAKOSHI, J, LI, Y. P, SHUNG, B, TAKEBE, H, ABE, M

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Quasi-pushout cell discarding von Yu-Sheng Lin, Shung, C.B.

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Queue management for shared buffer and shared multi-buffer ATM switches von Yu-Sheng Lin, Shung, C.B.

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TWI810885B von LIAO, TANG, HSIAO, YUIH, CHEN, SHIHING, LAI, JUN-LIANG, LIN, SHUNG-BO, HSIEH, KUN-HAN

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