CHISEL flash EEPROM - Part I: Performance and scaling von Shukuri, S, Mahapatra, Souvik, Bude, Jeff

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Drain disturb during CHISEL programming of NOR flash EEPROMs-physical mechanisms and impact of technological parameters von Nair, D.R., Mahapatra, S., Shukuri, S., Bude, J.D.

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CHISEL flash EEPROM - Part II: Reliability von Shukuri, S, Mahapatra, Souvik, Bude, Jeff

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CHISEL flash EEPROM. I. Performance and scaling von Mahapatra, S., Shukuri, S., Bude, J.

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Explanation of P/E cycling impact on drain disturb in flash EEPROMs under CHE and CHISEL programming operation von Nair, D.R., Mahapatra, S., Shukuri, S., Bude, J.D.

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Cycling endurance of NOR flash EEPROM cells under CHISEL programming operation - impact of technological parameters and scaling von Nair, D.R., Shukuri, S., Mahapatra, S.

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CHISEL flash EEPROM. II. Reliability von Mahapatra, S., Shukuri, S., Bude, J.

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CHISEL programming operation of scaled NOR flash EEPROMs-effect of voltage scaling, device scaling and technological parameters von Mohapatra, N.R., Nair, D.R., Mahapatra, S., Ramgopal Rao, V., Shukuri, S., Bude, J.D.

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A system LSI memory redundancy technique using an ie-flash (inverse-gate-electrode flash) programming circuit von Yamaoka, M., Yanagisawa, K., Shukuri, S., Norisue, K., Ishibashi, K.

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Crystallographic Analysis of Ground and Space Thermostable T1 Lipase Crystal Obtained via Counter Diffusion Method Approach von Mohamad Aris, Sayangku Nor Ariati, Thean Chor, Adam Leow, Mohamad Ali, Mohd Shukuri, Basri, Mahiran, Salleh, Abu Bakar, Raja Abd. Rahman, Raja Noor Zaliha

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Substrate bias effect on cycling induced performance degradation of flash EEPROMs von Mahapatra, S., Shukuri, S., Bude, J.

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Performance and Reliability of High Density Flash EEPROMs under CHISEL Programming Operation von Mahapatra, S., Shukuri, S., Bude, J.

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A semi-static complementary gain cell technology for sub-1 V supply DRAM's von Shukuri, S., Kure, T., Kobayashi, T., Gotoh, Y., Nishida, T.

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256-Mb DRAM circuit technologies for file applications von Kitsukawa, G., Horiguchi, M., Kawajiri, Y., Kawahara, T., Akiba, T., Kawase, Y., Tachibana, T., Sakai, T., Aoki, M., Shukuri, S., Sagara, K., Nagai, R., Ohji, Y., Hasegawa, N., Yokoyama, N., Kisu, T., Yamashita, H., Kure, T., Nishida, T.

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The impact of channel engineering on the performance reliability and scaling of CHISEL NOR flash EEPROMs von Mohapatra, N.R., Nair, D.R., Mahapatra, S., Rao, V.R., Shukuri, S.

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A True 6F2 NOR Flash Memory Cell Technology - Impact of Floating Gate B4-Flash on NOR Scaling von Shimizu, S, Shukuri, S, Ajika, N, Ogura, T, Mihara, M, Kawajiri, Y, Kobayashi, K, Nakashima, M

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Highly Reliable B4-Flash Technology for High Density Embedded NVM Application von Ajika, N, Shukuri, S, Shimizu, S, Ogura, T, Mihara, M, Kobayashi, K, Nakashima, M

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Quasi-complementary BiCMOS for sub-3-V digital circuits von Yano, K., Hiraki, M., Shukuri, S., Onose, Y., Hirao, M., Ohki, N., Nishida, T., Seki, K., Shimohigashi, K.

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Focused ion beam gallium implantation into silicon von Tamura, M., Shukuri, S., Moniwa, M., Default, M.

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3.3-V BiCMOS circuit techniques for 250-MHz RISC arithmetic modules von Yano, K., Hiraki, M., Shukuri, S., Hanawa, M., Suzuki, M., Morita, S., Kawamata, A., Ohki, N., Nishida, T., Seki, K.

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