A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition von Guanghua Shu, Woo-Seok Choi, Saxena, Saurabh, Talegaonkar, Mrunmay, Anand, Tejasvi, Elkholy, Ahmed, Elshazly, Amr, Hanumolu, Pavan Kumar

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Low-Jitter Multi-Output All-Digital Clock Generator Using DTC-Based Open Loop Fractional Dividers von Elkholy, Ahmed, Saxena, Saurabh, Shu, Guanghua, Elshazly, Amr, Hanumolu, Pavan Kumar

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A 12-Gb/s -16.8-dBm OMA Sensitivity 23-mW Optical Receiver in 65-nm CMOS von Ahmed, Mostafa Gamal, Talegaonkar, Mrunmay, Elkholy, Ahmed, Guanghua Shu, Elmallah, Ahmed, Rylyakov, Alexander, Hanumolu, Pavan Kumar

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A 0.45-0.7 V 1-6 Gb/s 0.29-0.58 pJ/b Source-Synchronous Transceiver Using Near-Threshold Operation von Woo-Seok Choi, Guanghua Shu, Talegaonkar, Mrunmay, Yubo Liu, Da Wei, Benini, Luca, Hanumolu, Pavan Kumar

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A Burst-Mode Digital Receiver With Programmable Input Jitter Filtering for Energy Proportional Links von Woo-Seok Choi, Anand, Tejasvi, Guanghua Shu, Elshazly, Amr, Hanumolu, Pavan Kumar

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A 10-Gb/s/ch, 0.6-pJ/bit/mm Power Scalable Rapid-ON/OFF Transceiver for On-Chip Energy Proportional Interconnects von Da Wei, Anand, Tejasvi, Guanghua Shu, Schutt-Aine, Jose E., Hanumolu, Pavan Kumar

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A Reference-Less Clock and Data Recovery Circuit Using Phase-Rotating Phase-Locked Loop von Guanghua Shu, Saxena, Saurabh, Woo-Seok Choi, Talegaonkar, Mrunmay, Inti, Rajesh, Elshazly, Amr, Young, Brian, Hanumolu, Pavan Kumar

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A 2.8 mW/Gb/s, 14 Gb/s Serial Link Transceiver von Saxena, Saurabh, Guanghua Shu, Nandwana, Romesh Kumar, Talegaonkar, Mrunmay, Elkholy, Ahmed, Anand, Tejasvi, Woo-Seok Choi, Hanumolu, Pavan Kumar

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A 0.0021 mm2 1.82 mW 2.2 GHz PLL Using Time-Based Integral Control in 65 nm CMOS von Junheng Zhu, Nandwana, Romesh Kumar, Guanghua Shu, Elkholy, Ahmed, Seong Joong Kim, Hanumolu, Pavan Kumar

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8.7 A 4-to-10.5Gb/s 2.2mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS von Guanghua Shu, Woo-Seok Choi, Saxena, Saurabh, Anand, Tejasvi, Elshazly, Amr, Hanumolu, Pavan Kumar

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15.4 A 20-to-1000MHz ±14ps peak-to-peak jitter reconfigurable multi-output all-digital clock generator using open-loop fractional dividers in 65nm CMOS von Elkholy, Ahmed, Elshazly, Amr, Saxena, Saurabh, Guanghua Shu, Hanumolu, Pavan Kumar

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A 12-bit 50-MSPS SHA-less opamp-sharing Analog-to-Digital converter in 65nm CMOS von Chen Shu, Guanghua Shu, Jun Xu, Fan Ye, Junyan Ren

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A 12-bit 40-MS/s SHA-less pipelined ADC using a front-end RC matching technique von Fan, Mngjun (明俊 范), Ren, Junyan (俊彦 任), Shu, Guanghua (光华 舒), Guo, Yao (瑶过), Li, Ning (宁李), Ye, Fan (凡叶), Xu, Jun (俊许)

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A 0.0021 mm 2 1.82 mW 2.2 GHz PLL Using Time-Based Integral Control in 65 nm CMOS von Zhu, Junheng, Nandwana, Romesh Kumar, Shu, Guanghua, Elkholy, Ahmed, Kim, Seong Joong, Hanumolu, Pavan Kumar

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A 0.22 pJ/step subsampling ADC with fast input-tracking sampling and simplified opamp sharing von Guanghua Shu, Fan Ye, Yao Guo, Mingjun Fan, Junyan Ren, Jun Xu, Ning Li, Cheng Chen

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A power-efficient 10-bit 40-MS/s sub-sampling pipelined CMOS analog-to-digital converter von Shu, Guanghua, Guo, Yao, Ren, Junyan, Fan, Mingjun, Ye, Fan

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Feature Recommendations for Machine Learning Models Based on Feature-Model Co-Occurrences von Jensen, Jacob, Khanna, Sahil, Shu, Guanghua, Sadri, Reza

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Feature Recommendations for Machine Learning Models Using Trained Feature Prediction Model von Jensen, Jacob, Khanna, Sahil, Shu, Guanghua, Sadri, Reza

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GENERATING SESSION-BASED RECOMMENDATIONS USING LARGE LANGUAGE MACHINE-LEARNED MODELS von SINGH, Angadh, RAO, Young, RAO, Sharath, LIN, Brian, SHU, Guanghua

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A 12-bit 50-MS/s pipelined Analog-to-Digital Converter in 65nm CMOS von Guanghua Shu, Mingjun Fan, Chen Shu, Cheng Chen, Ning Li, Junyan Ren

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