Dopant profile and defect control in ion implantation by RTA with high ramp-up rate von Saito, S., Shishiguchi, S., Hamada, K., Hayashi, T.

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The reduction of grain size in LPCVD poly-Si by in situ oxygen and phosphorus doping von Shishiguchi, S., Okamoto, T., Arai, K., Hasebe, K., Shigematsu, N.

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Prediction of slip generation during rapid thermal processing von Higuchi, N, Matsumura, H, Watanabe, S, Shishiguchi, S

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Ultra Shallow Junction and Super Steep Halo Formation Using Carbon Co-implantation for 65nm High Performance CMOS Devices von Mineji, A., Shishiguchi, S.

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Rapid collection of X-ray powder data for pattern analysis by a cylindrical position-sensitive detector von Shishiguchi, S., Minato, I., Hashizume, H.

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Aggressive design of ultra-shallow junction for near-scaling-limit bulk planar CMOS by using raised source/drain extension structure and carbon co-implantion technology von Uejima, K, Yako, K, Yamamoto, T, Ikarashi, N, Shishiguchi, S, Hase, T, Hane, M

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Simulation of high-temperature millisecond annealing-based on atomistic modeling of boron diffusion/activation in silicon von Hane, M., Ikezawa, T., Matsuda, T., Shishiguchi, S.

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Optimized Source/Drain Ion Implantation Conditions for P-Channel Metal–Oxide–Semiconductor Field-Effect-Transistor Formation von Shishiguchi, Seiichi, Mineji, Akira, Matsuda, Tomoko

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Process and design of production-ready equipment for Cu line-pillar/low-k STP interconnect technology von Shishiguchi, S., Fukuda, T., Kochiya, H., Yanazawa, H.

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A novel method of removing impurities from multilevel interconnect materials von Fukuda, T., Shishiguchi, S., Yanazawa, H.

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Ultra Shallow Junction Formation with High Process Controllability Using Optimized Rapid Thermal Anneal Process von Matsuda, Tomoko, Shishiguchi, Seiichi, Kitajima, Hiroshi

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Phosphorus-Assisted Low-Energy Arsenic Implantation Technology for N-Channel Metal–Oxide–Semiconductor Field-Effect Transistor Source/Drain Formation Process von Imai, Kiyotaka, Shishiguchi, Seiichi, Shibahara, Kentaro, Yokoyama, Shin

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Low- k Dielectric Film Patterning by X-Ray Lithography von Kuroki, Shin-Ichiro, Kikkawa, Takamaro, Kochiya, Hiroyuki, Shishiguchi, Seiichi

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Borazine-siloxane organic/inorganic hybrid polymer von Inoue, M, Sekiyama, S, Nakamura, K, Shishiguchi, S, Matsuura, A, Fukuda, T, Yanazawa, H, Uchimaru, Y

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Lateral Diffusion Distance Measurement of 40–80 nm Junctions by Etching/TEM-Electron Energy Loss Spectroscopy Method von Kunimune, Yorinobu, Nishio, Naoharu, Kikuchi, NoriyukiKodama, Toda, Takeshi, Mineji, Akira, Shishiguchi, Seiichi, Saito, Shuichi

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Pushing Planar Bulk CMOSFET Scaling to its Limit by Ultimately Shallow Diffusion-Less Junction von Uejima, K., Yako, K., Ikarashi, N., Narihiro, M., Tanaka, M., Nagumo, T., Mineji, A., Shishiguchi, S., Hane, M.

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Comparison of Solid Phase Epi (SPE) non-melt to Liquid Phase Epi (LPE) melt laser annealing for 22nm node n+ USJ formation von Borland, J, Shishiguchi, S, Matsuzaka, N, Hane, M, Tanjyo, M, Oesterlini, P, Mayer, J

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Aggressive design of millisecond annealing junctions for near-scaling-limit bulk CMOS using raised source/drain extensions von Yako, K., Uejima, K., Yamamoto, T., Mineji, A., Nagumo, T., Ikezawa, T., Matsuzaka, N., Shishiguchi, S., Hase, T., Hane, M.

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NBTI Immune First Plasma Nitridation SiON with Multiple Single-Wafer Tools for 45nm node Gate Dielectrics von Tanaka, M., Koyama, S., Hasegawa, E., Olsen, C., Shishiguchi, S., Hane, M.

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Novel diffusion-less ultra-shallow junction engineering based on millisecond annealing for sub-30 nm gate length planar bulk CMOSFET von Uejima, K., Yako, K., Ikarashi, N., Narihiro, M., Tanaka, M., Nagumo, T., Mineji, A., Shishiguchi, S., Hane, M.

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