Nonvolatile Storage Cells Using FiCC for IoT Processors with Intermittent Operations von ABE, Yuki, KOBAYASHI, Kazutoshi, SHIOMI, Jun, OCHI, Hiroyuki

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Approximation-Based System Implementation for Real-Time Minimum Energy Point Tracking over a Wide Operating Performance Region von SONODA, Shoya, SHIOMI, Jun, ONODERA, Hidetoshi

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Approximate Minimum Energy Point Tracking and Task Scheduling for Energy-Efficient Real-Time Computing von KOMORI, Takumi, MASUDA, Yutaka, SHIOMI, Jun, ISHIHARA, Tohru

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Supply and Threshold Voltage Scaling for Minimum Energy Operation over a Wide Operating Performance Region von SONODA, Shoya, SHIOMI, Jun, ONODERA, Hidetoshi

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Evaluation Metrics for the Cost of Data Movement in Deep Neural Network Acceleration von XU, Hongjie, SHIOMI, Jun, ONODERA, Hidetoshi

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A DLL-Based Body Bias Generator with Independent P-Well and N-Well Biasing for Minimum Energy Operation von NAGAI, Kentaro, SHIOMI, Jun, ONODERA, Hidetoshi

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StrideHD: A Binary Hyperdimensional Computing System Utilizing Window Striding for Image Classification von Liang, Dehua, Shiomi, Jun, Miura, Noriyuki, Awano, Hiromitsu

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A Hardware Efficient Reservoir Computing System Using Cellular Automata and Ensemble Bloom Filter von LIANG, Dehua, SHIOMI, Jun, MIURA, Noriyuki, HASHIMOTO, Masanori, AWANO, Hiromitsu

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A Synthesis Method Based on Multi-Stage Optimization for Power-Efficient Integrated Optical Logic Circuits von MATSUO, Ryosuke, SHIOMI, Jun, ISHIHARA, Tohru, ONODERA, Hidetoshi, SHINYA, Akihiko, NOTOMI, Masaya

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Neural Network Calculations at the Speed of Light Using Optical Vector-Matrix Multiplication and Optoelectronic Activation von HATTORI, Naoki, SHIOMI, Jun, MASUDA, Yutaka, ISHIHARA, Tohru, SHINYA, Akihiko, NOTOMI, Masaya

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A Design Method of a Cell-Based Amplifier for Body Bias Generation von KOYANAGI, Takuya, SHIOMI, Jun, ISHIHARA, Tohru, ONODERA, Hidetoshi

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Area-efficient fully digital memory using minimum height standard cells for near-threshold voltage computing von Shiomi, Jun, Ishihara, Tohru, Onodera, Hidetoshi

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On-Chip Cache Architecture Exploiting Hybrid Memory Structures for Near-Threshold Computing von XU, Hongjie, SHIOMI, Jun, ISHIHARA, Tohru, ONODERA, Hidetoshi

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MOSDA: On-Chip Memory Optimized Sparse Deep Neural Network Accelerator With Efficient Index Matching von Xu, Hongjie, Shiomi, Jun, Onodera, Hidetoshi

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Methods for Reducing Power and Area of BDD-Based Optical Logic Circuits von MATSUO, Ryosuke, SHIOMI, Jun, ISHIHARA, Tohru, ONODERA, Hidetoshi, SHINYA, Akihiko, NOTOMI, Masaya

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A Necessary and Sufficient Condition of Supply and Threshold Voltages in CMOS Circuits for Minimum Energy Point Operation von SHIOMI, Jun, ISHIHARA, Tohru, ONODERA, Hidetoshi

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Statistical Timing Modeling Based on a Lognormal Distribution Model for Near-Threshold Circuit Optimization von SHIOMI, Jun, ISHIHARA, Tohru, ONODERA, Hidetoshi

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Analytical Stability Modeling for CMOS Latches in Low Voltage Operation von KAMAKARI, Tatsuya, SHIOMI, Jun, ISHIHARA, Tohru, ONODERA, Hidetoshi

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Real-time adaptive data transmission against various traffic load in multi-LIDAR sensor network for indoor monitoring von Akiyama, Kuon, Azuma, Kenta, Shinkuma, Ryoichi, Shiomi, Jun

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Approximation-Based System Implementation for Real-Time Minimum Energy Point Tracking over a Wide Operating Performance Region von SONODA, Shoya, SHIOMI, Jun, ONODERA, Hidetoshi

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