Dual-period self-refresh scheme for low-power DRAM's with on-chip PROM mode register von Idei, Y., Shimohigashi, K., Aoki, M., Noda, H., Iwai, H., Sato, K., Tachibana, T.

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Low-voltage ULSI design von Shimohigashi, K., Seki, K.

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Design and performance of 0.1- mu m CMOS devices using low-impurity-channel transistors (LICT's) von Aoki, M., Ishii, T., Yoshimura, T., Kiyota, Y., Iijima, S., Yamanaka, T., Kure, T., Ohyu, K., Nishida, T., Okazaki, S., Seki, K., Shimohigashi, K.

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A high-current-gain low-temperature pseudo-HBT utilizing a sidewall base-contact structure (SICOS) von Yano, K., Nakazato, K., Miyamoto, M., Aoki, M., Shimohigashi, K.

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An alpha -immune, 2-V supply voltage SRAM using a polysilicon PMOS load cell von Ishibashi, K., Yamanaka, T., Shimohigashi, K.

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Base-emitter injection characterization in low-temperature pseudo-heterojunction bipolar transistors von Yano, K., Nakazato, K., Miyamoto, M., Aoki, M., Shimohigashi, K.

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Quasi-complementary BiCMOS for sub-3-V digital circuits von Yano, K., Hiraki, M., Shukuri, S., Onose, Y., Hirao, M., Ohki, N., Nishida, T., Seki, K., Shimohigashi, K.

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Alpha-particle-induced charge collection measurements for megabit DRAM cells von Takeuchi, K., Shimohigashi, K., Takeda, E., Yamasaki, E., Toyabe, T., Itoh, K.

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An experimental large-capacity semiconductor file memory using 16-levels/cell storage von Horiguchi, M., Aoki, M., Nakagome, Y., Ikenaga, S., Shimohigashi, K.

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Fully symmetric cooled CMOS on (110) plane von AOKI, M, YANO, K, MASUHARA, T, SHIMOHIGASHI, K

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Origin and characteristics of alpha-particle-induced permanent junction leakage von Takeuchi, K., Shimohigashi, K., Kozuka, H., Toyabe, T., Itoh, K., Kurosawa, H.

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A feedback-type BiCMOS logic gate von Nishio, Y., Murabayashi, F., Kotoku, S., Watnabe, A., Shukuri, S., Shimohigashi, K.

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A 3.5-ns, 500-mW, 16-kbit BiCMOS ECL RAM von Suzuki, M., Tachibana, S., Watanabe, A., Shukuri, S., Higuchi, H., Nagano, T., Shimohigashi, K.

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A 65-ns 4-Mbit CMOS DRAM with a twisted driveline sense amplifier von Kimura, K., Shimohigashi, K., Etoh, J., Ishihara, M., Miyazawa, K., Shimizu, S., Sakai, Y., Yagi, K.

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Characteristics of a Buried-Channel Graded Drain with Punchthrough Stopper (BGP) MOS Device von Sunami, H., Shimohigashi, K., Hashimoto, N.

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Characteristics of a buried-channel graded drain with punchthrough stopper (BGP) MOS device von Sunami, H., Shimohigashi, K., Hashimoto, N.

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Improved planar isolation with buried-channel MOS FET's von Sunami, H., Kawamoto, Y., Shimohigashi, K., Hashimoto, N.

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An n-well CMOS dynamic RAM von Shimohigashi, K., Masuda, H., Kamigaki, Y., Itoh, K., Hashimoto, N., Arai, E.

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A high-speed 16-kbit n-MOS random-access memory von Itoh, K., Shimohigashi, K., Chiba, K., Taniguchi, K., Kawamoto, H.

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Fully symmetric cooled CMOS on von Aoki, M., Yano, K., Masuhara, T., Shimohigashi, K.

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