Bipolar Transistor Test Structures for Extracting Minority Carrier Lifetime in IGBTs von Takeuchi, Kiyoshi, Fukui, Munetoshi, Saraya, Takuya, Itou, Kazuo, Takakura, Toshihiko, Suzuki, Shinichi, Numasawa, Yohichiroh, Shigyo, Naoyuki, Kakushima, Kuniyuki, Hoshii, Takuya, Furukawa, Kazuyoshi, Watanabe, Masahiro, Wakabayashi, Hitoshi, Tsutsui, Kazuo, Iwai, Hiroshi, Ogura, Atsushi, Saito, Wataru, Nishizawa, Shin-Ichi, Tsukuda, Masanori, Omura, Ichiro, Ohashi, Hiromichi, Hiramoto, Toshiro

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A review of narrow-channel effects for STI MOSFET's: A difference between surface- and buried-channel cases von Shigyo, Naoyuki, Hiraoka, Takayuki

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Verification of overlap and fringing capacitance models for MOSFETs von Wakita, Naoki, Shigyo, Naoyuki

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Simple nondestructive extraction of the vertical channel-impurity profile of small-size metal–oxide–semiconductor field-effect transistors von Mattausch, Hans Jürgen, Suetake, Masami, Kitamaru, Daisuke, Miura-Mattausch, Mitiko, Kumashiro, Shigetaka, Shigyo, Naoyuki, Odanaka, Shinji, Nakayama, Noriaki

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An explicit expression for surface potential at high-end of moderate inversion von Shigyo, N.

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Calibration Method for High-Density-Plasma Chemical Vapor Deposition Simulation von Kinoshita, Shigeru, Takagi, Shigeyuki, Yabuhara, Hidehiko, Nishimura, Hiroshi, Kawaguchi, Hideichi, Shigyo, Naoyuki

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Tradeoff between interconnect capacitance and RC delay variations induced by process fluctuations von Shigyo, N.

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An analysis of process fluctuation induced propagation delay variation using analytical model von Shigyo, Naoyuki

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Counter-Doped Surface Channel Metal-Oxide-Semiconductor Field-Effect Transistor with High Current Drivability and Steep Subthreshold Slope von Koike, Hidetoshi, Enda, Toshiyuki, Matsuoka, Fumitomo, Shigyo, Naoyuki

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Alleviation of subthreshold swing and short-channel effect in buried-channel MOSFETs: The counter-doped surface-channel MOSFET structure von Enda, Toshiyuki, Shigyo, Naoyuki

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Analysis of Si-Ge source structure in 0.15 μm SOI MOSFETs using two-dimensional device simulation von ARISUMI, O, MATSUZAWA, K, SHIGYO, N, TERAUCHI, M, NISHIYAMA, A, YOSHIMI, M

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Analysis of Si–Ge Source Structure in 0.15 µm SOI MOSFETs Using Two-Dimensional Device Simulation von Arisumi, Osamu, Matsuzawa, Kazuya, Shigyo, Naoyuki, Terauchi, Mamoru, Akira Nishiyama, Akira Nishiyama, Makoto Yoshimi, Makoto Yoshimi

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Effects of microscopic fluctuations in dopant distributions on MOSFET threshold voltage von Nishinohara, K., Shigyo, N., Wada, T.

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A new quantum effect model for practical device simulation von Shigyo, N., Tanimoto, H.

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Mesh related problems in device simulation von Shigyo, Naoyuki, Tanimoto, Hiroyoshi, Enda, Toshiyuki

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NAND TYPE NONVOLATILE SEMICONDUCTOR MEMORY von SHIGYO NAOYUKI

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Mesh related problems in device simulation:: Treatments of meshing noise and leakage current von Shigyo, Naoyuki, Tanimoto, Hiroyoshi, Enda, Toshiyuki

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Technology CAD based statistical simulation of MOSFETs von Shigyo, Naoyuki, Wakita, Naoki, Morishita, Tetsuji, Sugawara, Kenichi, Asahi, Yoshinori

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"Depletion isolation effect" of surrounding gate transistors von Terauchi, M., Shigyo, N., Nitayama, A., Horiguchi, F.

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Semiconductor device including overcurrent protection element von SHIGYO NAOYUKI, WATANABE KENTARO

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