Coworker Exchange: Relationships Between Coworkers, Leader-Member Exchange, and Work Attitudes von Sherony, Kathryn M, Green, Stephen G

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Effect of SiGe channel on pFET variability in 32 nm technology von YUAN, X, ZHANG, Q, TRAN, H, FOX, S, SHERONY, M

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Effect of floating-body charge on SOI MOSFET design von Wei, A., Sherony, M.J., Antoniadis, D.A.

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Self-Annealing Effect of Tensile Liner on Thick-Tinv PMOS von Qintao Zhang, Jie Chen, Sherony, M. J.

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Effect of SiGe channel on pFET variability in 32 nm technology von Yuan, X, Zhang, Q, Tran, H, Fox, S, Sherony, M

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SOI MOSFET effective channel mobility von Sherony, M.J., Su, L.T., Chung, J.E., Antoniadis, D.A.

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PD/SOI SRAM performance in presence of gate-to-body tunneling current von Joshi, R.V., Ching-Te Chuang, Fung, S.K.H., Assaderaghi, F., Sherony, M., Yang, I., Shahidi, G.

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A 4-91-GHz traveling-wave amplifier in a standard 0.12-μm SOI CMOS microprocessor technology von PLOUCHART, Jean-Olivier, KIM, Jonghae, WAGNER, Lawrence F, ZAMDMER, Noah, LU, Liang-Hung, SHERONY, Melanie, YUE TAN, GROVES, Robert A, TRZCINSKI, Robert, TALBI, Mohamed, RAY, Asit

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Transient behavior of the kink effect in partially-depleted SOI MOSFET's von Wei, A., Sherony, M.J., Antoniadis, D.A.

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A cost effective 32nm high-K/ metal gate CMOS technology for low power applications with single-metal/gate-first process von Chen, X., Samavedam, S., Narayanan, V., Stein, K., Hobbs, C., Baiocco, C., Li, W., Jaeger, D., Zaleski, M., Yang, H. S., Kim, N., Lee, Y., Zhang, D., Kang, L., Chen, J., Zhuang, H., Sheikh, A., Wallner, J., Aquilino, M., Han, J., Jin, Z., Li, J., Massey, G., Kalpat, S., Jha, R., Moumen, N., Mo, R., Kirshnan, S., Wang, X., Chudzik, M., Chowdhury, M., Nair, D., Reddy, C., Teh, Y. W., Kothandaraman, C., Coolbaugh, D., Pandey, S., Tekleab, D., Thean, A., Sherony, M., Lage, C., Sudijono, J., Lindsay, R., Ku, J. H., Khare, M., Steegen, A.

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Silicon-on-insulator dynamic threshold ESD networks and active clamp circuitry von Voldman, S., Hui, D., Young, D., Williams, R., Dreps, D., Howard, J., Sherony, M., Assaderaghi, F., Shahidi, G.

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Suitability of Scaled SOI CMOS for High-Frequency Analog Circuits von Zamdmer, N., Plouchart, J.-O., Kim, J., Lu, L.-H., Narasimha, S., O'Neil, P., Ray, A., Sherony, M., Wagner, L.

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Reduction of threshold voltage sensitivity in SOI MOSFET's von Sherony, M.J., Su, L.T., Chung, J.E., Antoniadis, D.A.

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Process and local layout effect interaction on a high performance planar 20nm CMOS von Sato, F., Ramachandran, R., Van Meer, H., Cho, K. H., Ozbek, A., Yang, X., Liu, Y., Li, Z., Wu, X., Jain, S., Utomo, H., Kwon, U., Park, Y., Tan, W. L., Dai, X., Lai, W., Kim, J., Jones, D., Ganz, M., Bae, D. H., Lallement, R., Vemula, S. C., Kwon, T., Lee, P., Qi, Y., Weybright, M., Scholze, A., Bingert, R., King, J., Sherony, M., Eller, M., Shang, H., Tabakman, K., Narayanan, V., Samavedam, S., Divakaruni, R.

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Body voltage and history effect sensitivity to key device parameters in 90nm PD-SOI von KAWANAKA, S, KETCHEN, M. B, NII, H, HARIFUCHI, H, SUDO, G, RAUSCH, W, KIMURA, H, NAKAO, T, PARK, H, OH, S.-H, WAITE, A, WOMACK, S, BHUSHAN, M, NARASIMHA, S, MOCUTA, A. C, AJMERA, A, LI, Y, MALIK, R, KOHYAMA, Y, CHEEK, J, YANG, I, CLARK, W. F, DIVAKARUNI, R, PEARSON, D. J, BHASIN, R, MCSTAY, K, SHERONY, M, FISHER, P, MATSUMOTO, K, UTOMO, H

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32nm general purpose bulk CMOS technology for high performance applications at low voltage von Arnaud, F., Liu, J., Lee, Y.M., Lim, K.Y., Kohler, S., Chen, J., Moon, B.K., Lai, C.W., Lipinski, M., Sang, L., Guarin, F., Hobbs, C., Ferreira, P., Ohuchi, K., Li, J., Zhuang, H., Mora, P., Zhang, Q., Nair, D.R., Lee, D.H., Chan, K.K., Satadru, S., Yang, S., Koshy, J., Hayter, W., Zaleski, M., Coolbaugh, D.V., Kim, H.W., Ee, Y.C., Sudijono, J., Thean, A., Sherony, M., Samavedam, S., Khare, M., Goldberg, C., Steegen, A.

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PMOSFET layout dependency with embedded SiGe Source/Drain at POLY and STI edge in 32/28nm CMOS technology von Song, L., Liang, Y., Onoda, H., Lai, C. W., Wallner, T. A., Pofelski, A., Gruensfelder, C., Josse, E., Okawa, T., Brown, J., Williams, R. Q., Holt, J., Weijtmans, J. W., Greene, B., Utomo, H. K., Lee, S. C., Nair, D., Zhang, Q., Zhu, C., Wu, X., Sherony, M., Lee, Y. M., Henson, W. K., Divakaruni, R., Kaste, E.

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Advanced multi-high-operation-voltage I/O device design for 32nm gate-first HiK MG technology von Xusheng Wu, Hu, Y, Kusunoki, N, Yang, Z J, Yang, G, Teh, Y, Kirshnan, R, Krishnan, S, Shepard, J, Han, S, Lee, Y, Arnaud, F, Sherony, M, Sudijono, J, Steegen, A

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A 4-91-GHz traveling-wave amplifier in a standard 0.12-[micro]m SOI CMOS microprocessor technology von Plouchart, J.-O, Kim, Jonghae, Zamdmer, N, Lu, Liang-Hung, Sherony, M, Tan, Y, Groves, R.A, Trzcinski, R, Talbi, M, Ray, A, Wagner, L.F

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A 4-91-GHz traveling-wave amplifier in a standard 0.12-mum SOI CMOS microprocessor technology von Plouchart, J-O, Kim, Jonghae, Zamdmer, N, Lu, Liang-Hung, Sherony, M, Tan, Y, Groves, R A, Trzcinski, R, Talbi, M, Ray, A, Wagner, L F

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