Design Flow Allowing the Effective Use of Non-scan and Scan-Based Tests von Seinauskas, Rimantas

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Examination of the Possibilities for Integrated Testing of Embedded Systems von Seinauskas, Rimantas

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Possibilities for Unification of Hardware and Software Testing von Seinauskas, Rimantas, Seinauskas, Vytenis

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Functional Test Generation Based on Combined Random and Deterministic Search Methods von Bareiša, Eduardas, Jusas, Vacius, Motiejūnas, Kęstutis, Šeinauskas, Rimantas

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Acceleration of Fault Simulation based on a Separate List of Faults for each Test Pattern von Seinauskas, Rimantas, Cvirka, Ramunas

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Path delay test generation at functional level von Bareisa, Eduardas, Jusas, Vacius, Motiejunas, Kestutis, Seinauskas, Rimantas

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Delay fault testing using partial multiple scan chains von Bareisa, Eduardas, Jusas, Vacius, Motiejunas, Kestutis, Seinauskas, Rimantas

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Functional fault models for non-scan sequential circuits von Bareisa, Eduardas, Jusas, Vacius, Motiejunas, Kestutis, Seinauskas, Rimantas

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Functional delay test generation based on software prototype von Bareisa, Eduardas, Jusas, Vacius, Motiejunas, Kestutis, Seinauskas, Rimantas

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Test generation at the algorithm-level for gate-level fault coverage von Bareisa, Eduardas, Jusas, Vacius, Motiejunas, Kestutis, Seinauskas, Rimantas

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Development of Functional Delay Tests von Bareisa, Eduardas, Jusas, Vacius, Motiejunas, Kestutis, Seinauskas, Rimantas

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Transition Faults Testing Based on Functional Delay Tests von Bareisa, E., Jusas, V., Motiejunas, K., Seinauskas, R.

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The Realization-Independent Testing Based on the Black Box Fault Models von Bareiša, Eduardas, Jusas, Vacius, Motiejūnas, Kęstutis, Šeinauskas, Rimantas

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BLACK-BOX FAULT MODELS von Bareiša, Eduardas, Jusas, Vacius, Motiejūnas, Kęstutis, Šeinauskas, Rimantas

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Identifying Legal and Illegal States in Synchronous Sequential Circuits Using Test Generation von Bareiša, Eduardas, Motiejūnas, Kęstutis, Šeinauskas, Rimantas

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