A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier von Barth, J., Reohr, W.R., Parries, P., Fredeman, G., Golz, J., Schuster, S.E., Matick, R.E., Hunter, H., Tanner, C.C., Harig, J., Kim Hoki, Khan, B.A., Griesemer, J., Havreluk, R.P., Yanagisawa, K., Kirihata, T., Iyer, S.S.

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Fast Low Power eDRAM Hierarchical Differential Sense Amplifier von Schuster, S.E., Matick, R.E.

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Low-power synchronous-to-asynchronous- to-synchronous interlocked pipelined CMOS circuits operating at 3.3-4.5 GHz von Schuster, S.E., Cook, P.W.

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Power-aware microarchitecture: design and modeling challenges for next-generation microprocessors von Brooks, D.M., Bose, P., Schuster, S.E., Jacobson, H., Kudva, P.N., Buyuktosunoglu, A., Wellman, J., Zyuban, V., Gupta, M., Cook, P.W.

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Dynamically tuning processor resources with adaptive processing von Albonesi, D. H., Balasubramonian, R., Dropsbo, S. G., Dwarkadas, S., Friedman, E. G., Huang, M. C., Kursun, V., Magklis, G., Scott, M. L., Semeraro, G., Bose, P., Buyuktosunoglu, A., Cook, P. W., Schuster, S. E.

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Low-power synchronous-to-asynchronous-tosynchronous interlocked pipelined CMOS circuits operating at 3.3 - 4.5 GHz von Schuster, S.E., Cook, P.W.

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Stability and SER analysis of static RAM cells von Chappell, B., Schuster, S.E., Sai-Halasz, G.A.

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Synchronous interlocked pipelines von Jacobson, H.M., Kudva, P.N., Bose, P., Cook, P.W., Schuster, S.E., Mercer, E.G., Myers, C.J.

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A 2-ns cycle, 3.8-ns access 512-kb CMOS ECL SRAM with a fully pipelined architecture von Chappell, T.I., Chappell, B.A., Schuster, S.E., Allan, J.W., Klepner, S.P., Joshi, R.V., Franch, R.L.

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1 µm MOSFET VLSI technology: Part IV-Hot-electron design constraints von Ning, T.H., Cook, P.W., Dennard, R.H., Osburn, C.M., Schuster, S.E., Yu, H.

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Multiple word/bit line redundancy for semiconductor memories von Schuster, S.E.

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On-chip decoupling capacitor optimization for high-performance VLSI design von Chen, H.H., Schuster, S.E.

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On-chip test circuitry for a 2-ns cycle, 512-kb CMOS ECL SRAM von Schuster, S.E., Chappell, T.I., Chappell, B.A., Franch, R.L.

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Fast CMOS ECL receivers with 100-mV worst-case sensitivity von Chappell, B.A., Chappell, T.I., Schuster, S.E., Segmuller, H.M., Allan, J.W., Franch, R.L., Restle, P.J.

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Stability and SER Analysis of Static RAM Cells von Chappell, B., Schuster, S.E., Sai-Halasz, G.A.

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1 /spl mu/m MOSFET VLSI technology. III. Logic circuit design methodology and applications von Cook, P.W., Schuster, S.E., Parrish, J.T., DiLonardo, V., Freedman, D.R.

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1 /spl mu/m MOSFET VLSI technology. IV. Hot-electron design constraints von Ning, T.H., Cook, P.W., Dennard, R.H., Osburn, C.M., Schuster, S.E.

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A 3.5 ns/77 K and 6.2 ns/300 K 64 K CMOS RAM with ECL interfaces von Chappell, T.I., Schuster, S.E., Chappell, B.A., Allan, J.W., Sun, J.Y., Klepner, S.P., Franch, S.P., Greier, P.F., Restle, P.J.

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1 µm MOSFET VLSI technology: Part III-Logic circuit design methodology and applications von Cook, P.W., Schuster, S.E., Parrish, J.T., DiLonardo, V., Freedman, D.R.

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A 20 ns 64K (4Kx16) NMOS RAM von Schuster, S.E., Chappell, B., Di Lonardo, V., Britton, P.E.

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