Low-temperature electron mobility in Trigate SOI MOSFETs von Colinge, J.-P., Quinn, A.J., Floyd, L., Redmond, G., Alderman, J.C., Weize Xiong, Cleavelin, C.R., Schulz, T., Schruefer, K., Knoblinger, G., Patruno, P.

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Impact of strained-silicon-on-insulator (sSOI) substrate on FinFET mobility von Xiong, W., Cleavelin, C.R., Kohli, P., Huffman, C., Schulz, T., Schruefer, K., Gebara, G., Mathews, K., Patruno, P., Le Vaillant, Y.-M., Cayrefourcq, I., Kennard, M., Mazure, C., Shin, K., Liu, T.-J.K.

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Temperature effects on trigate SOI MOSFETs von Colinge, J.-P., Floyd, L., Quinn, A.J., Redmond, G., Alderman, J.C., Xiong, W., Cleavelin, C.R., Schulz, T., Schruefer, K., Knoblinger, G., Patruno, P.

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The effects of fluorine on parametrics and reliability in a 0.18-μm 3.5/6.8 nm dual gate oxide CMOS technology von Hook, T B, Adler, E, Guarin, F, Lukaitis, J, Rovedo, N, Schruefer, K

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Study of bending-induced strain effects on MuGFET performance von Shin, K., Weize Xiong, Chung Yeung Cho, Cleavelin, C.R., Schulz, T., Schruefer, K., Patruno, P., Smith, L., Tsu-Jae King Liu

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Design and evaluation of basic analog circuits in an emerging MuGFET technology von Knoblinger, G., Kuttner, F., Marshall, A., Russ, C., Haibach, P., Patruno, P., Schulz, T., Xiong, W., Gostkowski, M., Schruefer, K., Cleavelin, C.R.

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Retention characteristics of zero-capacitor RAM (Z-RAM) cell based on FinFET and tri-gate devices von Bassin, C., Fazan, P., Xiong, W., Cleavelin, C.R., Schulz, T., Schruefer, K., Gostkowski, M., Patruno, P., Maleville, C., Nagoga, M., Okhonin, S.

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Radiation Dose Effects in Trigate SOI MOS Transistors von Colinge, J. P., Orozco, A., Rudee, J., Xiong, Weize, Cleavelin, C. Rinn, Schulz, T., Schrufer, K., Knoblinger, G., Patruno, P.

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Room-Temperature Low-Dimensional Effects in Pi-Gate SOI MOSFETs von Colinge, J.P., Weize Xiong, Cleavelin, C.R., Schulz, T., Schrufer, K., Matthews, K., Patruno, P.

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A Low-Power Multi-Gate FET CMOS Technology with 13.9ps Inverter Delay, Large-Scale Integrated High Performance Digital Circuits and SRAM von von Arnim, K., Augendre, E., Pacha, A.C., Schulz, T., San, K.T., Bauer, F., Nackaerts, A., Rooyackers, R., Vandeweyer, T., Degroote, B., Collaert, N., Dixit, A., Singanamalla, R., Xiong, W., Marshall, A., Cleavelin, C.R., Schrufer, K., Jurczak, M.

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Mechanism of Threshold Voltage Shift (Δ V th ) Caused by Negative Bias Temperature Instability (NBTI) in Deep Submicron pMOSFETs von Liu, Chuan-Hsi, Lee, Ming T., Lin, Chih-Yung, Chen, Jenkon, Loh, Y. T., Liou, Fu-Tai, Schruefer, Klaus, Katsetos, Anastasios A., Yang, Zhijian, Rovedo, Nivo, Hook, Terence B., Wann, Clement, Chen, Tze-Chiang

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Intrinsic Advantages of SOI Multiple-Gate MOSFET (MuGFET) for Low Power Applications von Xiong, Weize W., Cleavelin, C. Rinn, Hsu, Che-Hua, Ma, Mike, Schruefer, Klaus, Von Arnim, Klaus, Schulz, Thomas, Cayrefourcq, Ian, Mazure, Carlos, Patruno, Paul, Kennard, Mark, Shin, Kyoungsub, Xin, Sun, King Liu, Tsu-Jae, Cherkaoui, Karim, Colinge, J.P.

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Efficiency of low-power design techniques in Multi-Gate FET CMOS Circuits von Pacha, C., von Arnim, K., Bauer, F., Schulz, T., Xiong, W., San, K.T., Marshall, A., Baumann, T., Cleavelin, C.-R., Schruefer, K., Berthold, J.

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The effects of fluorine on parametrics and reliability in a 0.18-/spl mu/m 3.5/6.8 nm dual gate oxide CMOS technology von Hook, T.B., Adler, E., Guarin, F., Lukaitis, J., Rovedo, N., Schruefer, K.

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The effects of fluorine on parametrics and reliability in a0.18-mu m 3.5/6.8 nm dual gate oxide CMOS technology von Hook, T B, Adler, E, Guarin, F, Lukaitis, J, Rovedo, N, Schruefer, K

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The effects of fluorine on parametrics and reliability in a 0.18-[mu]m 3.5/6.8 nm dual gate oxide CMOS technology von Hook, T.B, Adler, E, Guarin, F, Lukaitis, J, Rovedo, N, Schruefer, K

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Self Heating Simulation of Multi-Gate FETs von Molzer, W., Schulz, T., Xiong, W., Cleavelin, R.C., Schrufer, K., Marshall, A., Matthews, K., Sedlmeir, J., Siprak, D., Knoblinger, G., Bertolissi, L., Patruno, P., Colinge, J.-P.

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Multi-Gate SOI MOSFET Operations in Harsh Environments von Xiong, W., Cleavelin, C.R., Hsu, C.H., Ma, M., Schulz, T., Schruefer, K., Patruno, P., Colinge, J.P.

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Analog design challenges and trade-offs using emerging materials and devices von Fulde, M., Mercha, A., Gustin, C., Parvais, B., Subramanian, V., Arnim, K.v., Bauer, F., Schruefer, K., Schmitt-Landsiedel, D., Knoblinger, G.

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Analog design challenges and trade-offs using emerging materials and devices von Fulde, M., Knoblinger, G., Mercha, A., Gustin, C., Parvais, B., Subramanian, V., Arnim, K. v., Bauer, F., Schruefer, K., Schmitt-Landsiedel, D.

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