Embedded computer architecture and automation von Ramakrishna Rau, B., Schlansker, M.S.

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EPIC: Explicitly Parallel Instruction Computing von Schlansker, M.S., Rau, B.R.

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Register allocation for software pipelined loops von Rau, B. R., Lee, M., Tirumalai, P. P., Schlansker, M. S.

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Parallelization of WHILE loops on pipelined architectures von TIRUMALAI, P. P, MENG LEE, SCHLANSKER, M. S

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Compiling for EPIC architectures von Kathail, V., Schlansker, M.S., Rau, B.R.

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Register allocation for software pipelined loops von Rau, B R, Lee, M, Tirumalai, P P, Schlansker, M S

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Sentinel scheduling: a model for compiler-controlled speculative execution von Mahlke, Scott A., Chen, William Y., Bringmann, Roger A., Hank, Richard E., Hwu, Wen-Mei W., Rau, B. Ramakrishna, Schlansker, Michael S.

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Sentinel scheduling: a model for compiler-controlled speculative execution: Architectural support for programming languages and systems von MAHLKE, S. A, CHEN, W. Y, BRINGMANN, R. A, HANK, R. E, HWU, W.-M. W, RAMAKRISHNA RAU, B, SCHLANSKER, M. S

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Addendum to Sparse Matrix Compiler Manual von Calahan,D. A, Schlansker,M. S

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Sentinel scheduling for VLIW and superscalar processors von Mahlke, Scott A., Chen, William Y., Hwu, Wen-mei W., Rau, B. Ramakrishna, Schlansker, Michael S.

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Bitwidth cognizant architecture synthesis of custom hardware accelerators von Mahlke, S., Ravindran, R., Schlansker, M., Schreiber, R., Sherwood, T.

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Killer Fabrics for Scalable Datacenters von Schlansker, M, Tourrilhes, J, Turner, Y, Santos, J R

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Exploiting Fine-Grained Data Parallelism with Chip Multiprocessors and Fast Barriers von Sampson, Jack, Gonzalez, Ruben, Collard, Jean-Francois, Jouppi, Norman P., Schlansker, Mike, Calder, Brad

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A distributed control path architecture for VLIW processors von Hongtao Zhong, Fan, K., Mahlke, S., Schlansker, M.

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Challenges to combining general-purpose and multimedia processors von Conte, T.M., Dubey, P.K., Jennings, M.D., Lee, R.B., Peleg, A., Rathnam, S., Schlansker, M., Song, P., Wolfe, A.

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Path-synchronous performance monitoring of interconnection networks based on source code attribution von Chabbi, Milind M, Yoga, Adarsh, Schlansker, Michael

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Compilers for instruction-level parallelism von Schlansker, M., Conte, T.M., Dehnert, J., Ebcioglu, K., Fang, J.Z., Thompson, C.L.

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Critical path reduction for scalar programs von Schlansker, M., Kathail, V.

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PATH-SYNCHRONOUS PERFORMANCE MONITORING OF INTERCONNECTION NETWORKS BASED ON SOURCE CODE ATTRIBUTION von Chabbi, Milind M, Yoga, Adarsh, Schlansker, Michael

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Ensemble routing for datacenter networks von Schlansker, M, Turner, Y, Tourrilhes, J, Karp, A

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