Influence of hydrogen on strain localization and fracture behavior in Al Zn Mg Cu aluminum alloys von Su, Hang, Toda, Hiroyuki, Masunaga, Ryohei, Shimizu, Kazuyuki, Gao, Hongye, Sasaki, Katsuro, Bhuiyan, Md Shahnewaz, Uesugi, Kentaro, Takeuchi, Akihisa, Watanabe, Yoshio

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Influence of hydrogen on strain localization and fracture behavior in AlZnMgCu aluminum alloys von Su, Hang, Toda, Hiroyuki, Masunaga, Ryohei, Shimizu, Kazuyuki, Gao, Hongye, Sasaki, Katsuro, Bhuiyan, Md Shahnewaz, Uesugi, Kentaro, Takeuchi, Akihisa, Watanabe, Yoshio

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KEY-OFF PUMP LOADING STRUCTURE von SASAKI KATSURO

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Trends in low-power RAM circuit technologies von Itoh, K., Sasaki, K., Nakagome, Y.

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A 1.5-ns 32-b CMOS ALU in double pass-transistor logic von Suzuki, M., Ohkubo, N., Shinbo, T., Yamanaka, T., Shimizu, A., Sasaki, K., Nakagome, Y.

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Half-swing clocking scheme for 75% power saving in clocking circuitry von Kojima, H., Tanaka, S., Sasaki, K.

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Instruction buffering to reduce power in processors for signal processing von Bajwa, R.S., Hiraki, M., Kojima, H., Gorny, D.J., Nitta, K., Shridhar, A., Seki, K., Sasaki, K.

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High-speed, low-voltage design for high-performance static RAMs von Sasaki, K.

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Current reliability issues and future technologies for systems on silicon – processes, circuits, chip architecture, and design von Takeda, Eiji, Watanabe, Takao, Kimura, Shinichiro, Yugami, Jiro, Haraguchi, Keiichi, Suzuki, Kei, Sasaki, Katsuro

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Advanced TFT SRAM cell technology using a phase-shift lithography von Yamanaka, T., Hashimoto, T., Hasegawa, N., Tanaka, T., Hashimoto, N., Shimizu, A., Ohki, N., Ishibashi, K., Sasaki, K., Nishida, T., Mine, T., Takeda, E., Nagano, T.

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A voltage down converter with submicroampere standby current for low-power static RAMs von Ishibashi, K., Sasaki, K., Toyoshima, H.

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A 1-V TFT-load SRAM using a two-step word-voltage method von Ishibashi, K., Takasugi, K., Hashimoto, T., Sasaki, K.

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A 7-ns 140-mW 1-Mb CMOS SRAM with current sense amplifier von Sasaki, K., Ishibashi, K., Ueda, K., Komiyaji, K., Yamanaka, T., Hashimoto, N., Toyoshima, H., Kojima, F., Shimizu, A.

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A 1.5-V full-swing BiCMOS logic circuit von Hiraki, M., Uano, K., Minami, M., Sato, K., Matsuzaki, N., Watanabe, A., Nishida, T., Sasaki, K., Seki, K.

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A 2.6-ns wave-pipelined CMOS SRAM with dual-sensing-latch circuits von Tachibana, S., Higuchi, H., Takasugi, K., Sasaki, K., Yamanaka, T., Nakagome, Y.

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16-Mb CMOS SRAM with a 2.3- mu m super(2) single-bit-line memory cell von Sasaki, Katsuro, Ueda, Kiyotsugu, Takasugi, Koichi, Toyoshima, Hiroshi, Ishibashi, Koichiro, Yamanaka, Toshiaki, Hashimoto, Naotaka, Ohki, Nagatoshi

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A 12.5-ns 16-Mb CMOS SRAM with common-centroid-geometry-layout sense amplifiers von Ishibashi, K., Komiyaji, K., Morita, S., Aoto, T., Ikeda, S., Asayama, K., Koike, A., Yamanaka, T., Hashimoto, N., Iida, H., Kojima, F., Motohashi, K., Sasaki, K.

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WORD LINE DRIVE CIRCUIT von SASAKI KATSURO

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STATIC TYPE RAM von SASAKI KATSURO

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SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD von SUGAI TAKAYASU, SASAKI KATSURO, HORIUCHI HITOSHI

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