FPGA Implementation of a Resource Efficient Vedic Multiplier using SPST Adders von Gowreesrinivas, K. V., Srinivas, Sabbavarapu, Samundiswary, Punniakodi

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Implementation of a Finite Impulse Response Filter using PUFs to Avoid Trojans von Bukke, Balaji Naik, Manjunathachari, Kamsali, Sabbavarapu, Srinivas

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Intellectual Property Design with PUF-based Hardware Security von Podugu, Devi Pradeep, Kamala Kumari, A., Sabbavarapu, Srinivas

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Fast 3D Integrated Circuit Placement Methodology using Merging Technique von Sabbavarapu, Srinivas, Acharyya, Amit, Balasubramanian, P., Reddy, C. Ramesh

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Flexible scan architecture von Jaber, Talal, Patil, Srinivas, Thatcher, Larry, Lin, Chih-Jen, Sabbavarapu, Anil, Wu, David, Reddy, Madhukar

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Flexible scan architecture von JABER TALAL K, PATIL SRINIVAS, SABBAVARAPU ANIL K, THATCHER LARRY E, WU DAVID M, REDDY MADHUKAR K, LIN CHIH-JEN M

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Flexible scan architecture von JABER TALAL K, PATIL SRINIVAS, SABBAVARAPU ANIL K, THATCHER LARRY E, WU DAVID M, REDDY MADHUKAR K, LIN CHIH-JEN M

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Flexible scan architecture von Jaber, Talal K, Patil, Srinivas, Thatcher, Larry E, Lin, Chih-Jen M, Sabbavarapu, Anil K, Wu, David M, Reddy, Madhukar K

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Flexible scan architecture von JABER TALAL K, PATIL SRINIVAS, SABBAVARAPU ANIL K, THATCHER LARRY E, WU DAVID M, REDDY MADHUKAR K, LIN CHIH-JEN M

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