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  1. 1
    System level hardware mechanisms for dynamic assist control

    System level hardware mechanisms for dynamic assist control von Kulshrestha, Narayan, V, Ramachandiran, Lee, Ka Yun, Smith, Brian, Sundararajan, Anand Shanmugam, Swarna, Madhukiran V, Wilder, Kevin

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  2. 2
    SYSTEM LEVEL HARDWARE MECHANISMS FOR DYNAMIC ASSIST CONTROL

    SYSTEM LEVEL HARDWARE MECHANISMS FOR DYNAMIC ASSIST CONTROL von LEE, Ka Yun, V, Ramachandiran, SUNDARARAJAN, Anand Shanmugam, SMITH, Brian, SWARNA, Madhukiran V, WILDER, Kevin, KULSHRESTHA, Narayan

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  3. 3
    Clock gating coupled memory retention circuit

    Clock gating coupled memory retention circuit von V, Ramachandiran, Srinivasaiah, Archana, Idgunji, Sachin, Chandratre, Abhijeet, Sundararajan, Anand Shanmugam, Yue, Lordson

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  4. 4
    CLOCK GATING COUPLED MEMORY RETENTION CIRCUIT

    CLOCK GATING COUPLED MEMORY RETENTION CIRCUIT von V, Ramachandiran, IDGUNJI, Sachin, SUNDARARAJAN, Anand Shanmugam, YUE, Lordson, SRINIVASAIAH, Archana, CHANDRATRE, Abhijeet

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  5. 5
    System-Level-Hardwaremechanismen für Dynamik-Assistenzsteuerung

    System-Level-Hardwaremechanismen für Dynamik-Assistenzsteuerung von Kulshrestha, Narayan, V, Ramachandiran, Lee, Ka Yun, Smith, Brian, Sundararajan, Anand Shanmugam, Swarna, Madhukiran V, Wilder, Kevin

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