Reliability enhancement due to in-situ post-oxidation of sputtered MgO barrier in double MgO barrier magnetic tunnel junction von Yoshida, Chikako, Noshiro, Hideyuki, Yamazaki, Yuichi, Sugii, Toshihiro

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Micromagnetic simulation of electric-field-assisted magnetization switching in perpendicular magnetic tunnel junction von Yoshida, Chikako, Noshiro, Hideyuki, Yamazaki, Yuichi, Sugii, Toshihiro, Tanaka, Tomohiro, Furuya, Atsushi, Uehara, Yuji

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Electrical-field and spin-transfer torque effects in CoFeB/MgO-based perpendicular magnetic tunnel junction von Yoshida, Chikako, Noshiro, Hideyuki, Yamazaki, Yuichi, Sugii, Toshihiro, Furuya, Atsushi, Ataka, Tadashi, Tanaka, Tomohiro, Uehara, Yuji

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Magnetic tunnel junctions for magnetic field sensor by using CoFeB sensing layer capped with MgO film von Takenaga, Takashi, Tsuzaki, Yosuke, Yoshida, Chikako, Yamazaki, Yuichi, Hatada, Akiyoshi, Nakabayashi, Masaaki, Iba, Yoshihisa, Takahashi, Atsushi, Noshiro, Hideyuki, Tsunoda, Koji, Aoki, Masaki, Furukawa, Taisuke, Fukumoto, Hiroshi, Sugii, Toshihiro

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A Counter-based Read Circuit Tolerant to Process Variation for 0.4-V Operating STT-MRAM von Umeki, Yohei, Yanagida, Koji, Yoshimoto, Shusuke, Izumi, Shintaro, Yoshimoto, Masahiko, Kawaguchi, Hiroshi, Tsunoda, Koji, Sugii, Toshihiro

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STT-MRAM Operating at 0.38V Using Negative-Resistance Sense Amplifier von UMEKI, Yohei, YANAGIDA, Koji, YOSHIMOTO, Shusuke, IZUMI, Shintaro, YOSHIMOTO, Masahiko, KAWAGUCHI, Hiroshi, TSUNODA, Koji, SUGII, Toshihiro

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Correlation between microstructure and electromagnetic properties in magnetic tunnel junctions with naturally oxidized MgO barrier von Yoshida, Chikako, Ochiai, Takao, Sugii, Toshihiro

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Advanced Input/Output Technology Using Laterally Modulated Channel Metal–Oxide–Semiconductor Field Effect Transistor for 65-nm Node System on a Chip von Yoshida, Eiji, Momiyama, Youichi, Hasegawa, Nobumasa, Kojima, Manabu, Satoh, Shigeo, Sugii, Toshihiro

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Enhanced Thermal Stability in Perpendicular Top-Pinned Magnetic Tunnel Junction With Synthetic Antiferromagnetic Free Layers von Yoshida, Chikako, Aoki, Masaki, Sugii, Toshihiro, Takenaga, Takashi, Iba, Yoshihisa, Yamazaki, Yuichi, Noshiro, Hideki, Tsunoda, Koji, Hatada, Akiyoshi, Nakabayashi, Masaaki, Takahashi, Atsushi

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Micromagnetic study of current-pulse-induced magnetization switching in magnetic tunnel junctions with antiferromagnetically and ferromagnetically coupled synthetic free layers von Yoshida, Chikako, Min Lee, Young, Ochiai, Takao, Uehara, Yuji, Sugii, Toshihiro

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Enhanced Reliability of Top-pinned Perpendicular Magnetic Tunnel Junction by Post-oxidation of Sputtered MgO Barrier von Yoshida, Chikako, Noshiro, Hideyuki, Yamazaki, Yuichi, Sugii, Toshihiro

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Toward Sub-20 nm Magnetic Tunnel Junction for Embedded Cache Memory von Yamazaki, Yuichi, Yoshida, Chikako, Sugii, Toshihiro, Iba, Yoshihisa, Noshiro, Hideyuki

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Reduction of Offset Field in Top-Pinned MTJ With Synthetic Antiferromagnetic Free Layer von Yoshida, Chikako, Takenaga, Takashi, Yamazaki, Yuichi, Uehara, Haruka, Noshiro, Hideyuki, Tsunoda, Koji, Iba, Yoshihisa, Hatada, Akiyoshi, Nakabayashi, Masaaki, Takahashi, Atsushi, Aoki, Masaki, Sugii, Toshihiro

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Reliability study of magnetic tunnel junction with naturally oxidized MgO barrier von Yoshida, C., Sugii, T.

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Thermal budget for fabricating a dual gate deep-submicron CMOS with thin pure gate oxide von SUZUKI, K, SATOH, A, AOYAMA, T, NAMURA, I, INOUE, F, KATAOKA, Y, TADA, Y, SUGII, T

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Impact ionization in 0.1 μm metal-oxide-semiconductor field-effect transistors von KURATA, H, NARA, Y, SUGII, T

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Integration of STT-MRAMs for Embedded Cache Memories von Noshiro, Hideyuki, Yoshida, Chikako, Takahashi, Atsushi, Yamazaki, Yuuichi, Iba, Yoshihisa, Hatada, Akiyoshi, Sugii, Toshihiro, Nakabayashi, Masaaki, Aoki, Masaki, Tsunoda, Kouji

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Highly scalable STT-MRAM with MTJs of top-pinned structure in 1T/1MTJ cell von Young Min Lee, Yoshida, C, Tsunoda, K, Umehara, S, Aoki, M, Sugii, T

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A thermal activation view of low voltage impact ionization in MOSFETs von Pin Su, Goto, K., Sugii, T., Chenming Hu

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Dynamic threshold pass-transistor logic for improved delay at lower power supply voltages von Lindert, N., Sugii, T., Tang, S., Chenming Hu

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