A Survey of Deep Learning on CPUs: Opportunities and Co-Optimizations von Mittal, Sparsh, Rajput, Poonam, Subramoney, Sreenivas

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PrxCa1−xMnO3 based stochastic neuron for Boltzmann machine to solve “maximum cut” problem von Khilwani, Devesh, Moghe, Vineet, Lashkare, Sandip, Saraswat, Vivek, Kumbhare, Pankaj, Shojaei Baghini, Maryam, Jandhyala, Srivatsava, Subramoney, Sreenivas, Ganguly, Udayan

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Early Prediction of DNN Activation Using Hierarchical Computations von Suresh, Bharathwaj, Pillai, Kamlesh, Kalsi, Gurpreet Singh, Abuhatzera, Avishaii, Subramoney, Sreenivas

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Enhanced regularization for on-chip training using analog and temporary memory weights von Singhal, Raghav, Saraswat, Vivek, Deshmukh, Shreyas, Subramoney, Sreenivas, Somappa, Laxmeesha, Baghini, Maryam Shojaei, Ganguly, Udayan

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Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning von Bera, Rahul, Kanellopoulos, Konstantinos, Nori, Anant V, Shahroodi, Taha, Sreenivas Subramoney, Mutlu, Onur

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Cooperative Multi-Agent Reinforcement Learning-Based Co-optimization of Cores, Caches, and On-chip Network von Jain, Rahul, Panda, Preeti Ranjan, Subramoney, Sreenivas

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A Unified Programmable Edge Matrix Processor for Deep Neural Networks and Matrix Algebra von George, Biji, Omer, Om Ji, Choudhury, Ziaul, V, Anoop, Subramoney, Sreenivas

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REAL: REquest Arbitration in Last Level Caches von Tiwari, Sakshi, Tuli, Shreshth, Ahmad, Isaar, Agarwal, Ayushi, Panda, Preeti Ranjan, Subramoney, Sreenivas

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ApHMM: Accelerating Profile Hidden Markov Models for Fast and Energy-efficient Genome Analysis von Firtina, Can, Pillai, Kamlesh, Kalsi, Gurpreet S., Suresh, Bharathwaj, Cali, Damla Senol, Kim, Jeremie S., Shahroodi, Taha, Cavlak, Meryem Banu, Lindegger, Joël, Alser, Mohammed, Luna, Juan Gómez, Subramoney, Sreenivas, Mutlu, Onur

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DSPatch: Dual Spatial Pattern Prefetcher von Bera, Rahul, Nori, Anant V, Mutlu, Onur, Sreenivas Subramoney

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Bypass and insertion algorithms for exclusive last-level caches von Gaur, Jayesh, Chaudhuri, Mainak, Subramoney, Sreenivas

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Micro-Sector Cache: Improving Space Utilization in Sectored DRAM Caches von Chaudhuri, Mainak, Agrawal, Mukesh, Gaur, Jayesh, Subramoney, Sreenivas

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Twig: Profile-Guided BTB Prefetching for Data Center Applications von Ahmed Khan, Tanvir, Brown, Nathan, Sriraman, Akshitha, Soundararajan, Niranjan, Kumar, Rakesh, Devietti, Joseph, Subramoney, Sreenivas, Pokam, Gilles, Litz, Heiner, Kasikci, Baris

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SeGraM: A Universal Hardware Accelerator for Genomic Sequence-to-Graph and Sequence-to-Sequence Mapping von Cali, Damla Senol, Kanellopoulos, Konstantinos, Lindegger, Joel, Bingöl, Zülal, Kalsi, Gurpreet S, Zuo, Ziyi, Firtina, Can, Cavlak, Meryem Banu, Kim, Jeremie, Nika Mansouri Ghiasi, Singh, Gagandeep, Gómez-Luna, Juan, Nour Almadhoun Alserr, Alser, Mohammed, Sreenivas Subramoney, Alkan, Can, Ghose, Saugata, Mutlu, Onur

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Pr x Ca 1 − x MnO 3 based stochastic neuron for Boltzmann machine to solve “maximum cut” problem von Khilwani, Devesh, Moghe, Vineet, Lashkare, Sandip, Saraswat, Vivek, Kumbhare, Pankaj, Shojaei Baghini, Maryam, Jandhyala, Srivatsava, Subramoney, Sreenivas, Ganguly, Udayan

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Taming Server Memory TCO with Multiple Software-Defined Compressed Tiers von Kumar, Sandeep, Prasad, Aravinda, Subramoney, Sreenivas

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Alternate path decode for hard-to-predict branch von Subramoney, Sreenivas, Soundararajan, Niranjan

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Restoring persistent application data from non-volatile memory after a system crash or system reboot von Subramoney, Sreenivas, Prasad, Aravinda

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DEVICE, METHOD AND SYSTEM TO CAPTURE OR RESTORE MICROARCHITECTURAL STATE OF A PROCESSOR CORE von Subramoney, Sreenivas, Soundararajan, Niranjan

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iMIV: in-Memory Integrity Verification for NVM von Jain, Rajat, Prasad, Aravinda, Subramoney, Sreenivas, Basu, Arkaprava

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