Converting thread-level parallelism to instruction-level parallelism via simultaneous multithreading von Lo, Jack L., Emer, Joel S., Levy, Henry M., Stamm, Rebecca L., Tullsen, Dean M., Eggers, S. J.

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Exploiting choice: instruction fetch and issue on an implementable simultaneous multithreading processor von Tullsen, Dean M., Eggers, Susan J., Emer, Joel S., Levy, Henry M., Lo, Jack L., Stamm, Rebecca L.

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Simultaneous multithreading: a platform for next-generation processors von Eggers, S.J., Emer, J.S., Levy, H.M., Lo, J.L., Stamm, R.L., Tullsen, D.M.

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Exploiting choice von Tullsen, Dean M, Eggers, Susan J, Emer, Joel S, Levy, Henry M, Lo, Jack L, Stamm, Rebecca L

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Method and apparatus for ordering read and write operations using conflict bits in a write queue von STAMM, REBECCA L

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A 100-MHz macropipelined VAX microprocessor von Badeau, R.W., Bahar, R.I., Bernstein, D., Biro, L.L., Bowhill, W.J., Brown, J.F., Case, M.A., Castelino, R.W., Cooper, E.M., Delaney, M.A., Deverell, D.R., Edmonson, J.H., Ellis, J.J., Fischer, T.C., Fox, T.F., Gowan, M.K., Gronowski, P.E., Herrick, W.V., Jain, A.K., Meyer, J.E., Miner, D.G., Partovi, H., Peng, V., Preston, R.P., Somanathan, C., Stamm, R.L., Thierauf, S.C., Uhler, G.M., Wade, N.D., Wheeler, W.R.

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Conversion of internal processor register commands to I/O space address von STAMM, REBECCA L, UHLER, MICHAEL G

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Conversion of internal processor register commands to I/O space addresses von UHLER, G. MICHAEL, STAMM, REBECCA L

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Processor and method for preventing access to a locked memory block by recording a lock in a content addressable memory with outstanding cache fills von WADE, NICHOLAS D, STAMM, REBECCA L

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CONVERSION OF INTERNAL PROCESSOR REGISTER COMMANDS TO I/O SPACE ADDRESS von STAMM, REBECCA L, UHLER, MICHAEL G

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Conversion of internal processor register commands to I/O space address von STAMM, REBECCA L, UHLER, MICHAEL G

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CONVERSION OF INTERNAL PROCESSOR REGISTER COMMANDS TO I/O SPACE ADDRESSES von UHLER, G. MICHAEL, STAMM, REBECCA L

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Method and apparatus for filtering invalidate requests von STAMM, REBECCA L, UHLER, MICHAEL G, DURDAN, HUGH W

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Processor and method for delaying the processing of cache coherency transactions during outstanding cache fills von BAHAR, RUTH I, WADE, NICHOLAS D, STAMM, REBECCA L

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METHOD AND APPARATUS FOR FILTERING INVALIDATE REQUESTS von UHLER, G. MICHAEL, DURDAN, W. HUGH, STAMM, REBECCA L

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Method and apparatus to quiesce a portion of a simultaneous multithreaded central processing unit von EMER JOEL S, EDWARDS BRUCE E, STAMM REBECCA L, FOSSUM TRYGGVE, REILLY MATTHEW H, ZILLES CRAIG B, HICKS JAMES E, JOERG CHRISTOPHER F

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METHOD AND APPARATUS FOR FILTERING INVALIDATE REQUESTS von UHLER, G. MICHAEL, STAMM, REBECCA L, DURDAN, W. HUGH

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METHOD AND APPARATUS FOR FILTERING INVALIDATE REQUESTS von STAMM, REBECCA L, UHLER, MICHAEL G, DURDAN, HUGH W

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Temporary halting of thread execution until monitoring of armed events to memory location identified in working registers von Emer, Joel S, Stamm, Rebecca L, Edwards, Bruce E, Reilly, Matthew H, Zilles, Craig B, Fossum, Tryggve, Joerg, Christopher F, Hicks, Jr., James E

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Temporary halting of thread execution until monitoring of armed events to memory location identified in working registers von EMER JOEL S, EDWARDS BRUCE E, STAMM REBECCA L, HICKS, JR. JAMES E, FOSSUM TRYGGVE, REILLY MATTHEW H, ZILLES CRAIG B, JOERG CHRISTOPHER F

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