Buried SiGe as a performance booster in n-channel FDSOI MOSFETs von Clifton, Paul, Goebel, Andreas, Mulfinger, Robert, Child, Amy, Straub, Sherry, Sporer, Ryan, Carter, Rick, Kluth, Jon, Schaeffer, Jamie, Nguyen, Bich-Yen, Chabanne, Guillaume, Daval, Nicolas, Schwarzenbach, Walter, Hemkar, Manish, Chu, Schubert, Moffatt, Steve

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(Invited) Extending Advanced CMOS Scaling with SiGe Channel Materials von Carter, Rick J, Sporer, Ryan, McArdle, Timothy J, Mulfinger, George Robert, Holt, Judson Robert, Beasor, Scott, Child, Amy, Fronheiser, Jody, Wahl, Jeremy A, Geisler, Holm, Kluth, George J, Triyoso, Dina H, Punchihewa, Kasun, Rana, Uzma, Vanamurthy, Laks, Sohn, D K

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(Invited) Factors Impacting Threshold Voltage in Advanced CMOS Integration: Gate Last (FINFET) vs. Gate First (FDSOI) von Triyoso, Dina, Carter, Rick, Kluth, Jon, Luning, Scott, Child, Amy, Wahl, Jeremy, Mulfinger, Bob, Punchihewa, Kasun, Kumar, Anil, Kang, Laegu, Sporer, Ryan, Chen, Xiaobo, Straub, Sherry, Bohra, Girish, Patil, Suraj, Zhang, Xing, Chen, Alex, Togo, Mitsuhiro, Pal, Rohit

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STRUCTURE INCLUDING HYBRID PLASMONIC WAVEGUIDE USING METAL SILICIDE LAYER von Sporer, Ryan William, Bian, Yusheng

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REFLECTORS FOR A PHOTONICS CHIP von Sporer, Ryan, Bian, Yusheng, Nummy, Karen

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A Process for Etching Modulated Profiles von Sporer, Ryan William, Landau, Uziel, Kuo, Hong-Hsiang Harry, Wang, Yar-Ming

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Optical components undercut by a sealed cavity von Sporer, Ryan, Bian, Yusheng, Hirokawa, Takako

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OPTICAL COMPONENTS UNDERCUT BY A SEALED CAVITY von Sporer, Ryan, Bian, Yusheng, Hirokawa, Takako

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PHOTONICS CHIPS INCLUDING A FULLY-DEPLETED SILICON-ON-INSULATOR FIELD-EFFECT TRANSISTOR von Sporer, Ryan, Mulfinger, George R, Bian, Yusheng

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PHOTONICS CHIPS INCLUDING A FULLY-DEPLETED SILICON-ON-INSULATOR FIELD-EFFECT TRANSISTOR von Sporer, Ryan, Mulfinger, George R, Bian, Yusheng

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Photonics chips including a fully-depleted silicon-on-insulator field-effect transistor von Sporer, Ryan, Mulfinger, George R, Bian, Yusheng

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Etch stop member in buried insulator of SOI substrate to reduce contact edge punch through von Shu, Jiehui, Sporer, Ryan W

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ETCH STOP MEMBER IN BURIED INSULATOR OF SOI SUBSTRATE TO REDUCE CONTACT EDGE PUNCH THROUGH von Shu, Jiehui, Sporer, Ryan W

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Technique for patterning active regions of transistor elements in a late manufacturing stage von Sporer, Ryan, Mulfinger, George

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TECHNIQUE FOR PATTERNING ACTIVE REGIONS OF TRANSISTOR ELEMENTS IN A LATE MANUFACTURING STAGE von Sporer, Ryan, Mulfinger, George

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A Novel Process for Etching Modulated Profiles von Sporer, Ryan William, Landau, Uziel, Kuo, Hong-Hsiang (Harry), Wang, Yar-Ming

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Well tap for an integrated circuit product and methods of forming such a well tap von Prabhu, Manjunatha, Ren, Hongru, Pritchard, David, Sporer, Ryan W

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Structure with different stress-inducing isolation dielectrics for different polarity FETs von Mulfinger, George R, Tan, Chung F, Sporer, Ryan W

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WELL TAP FOR AN INTEGRATED CIRCUIT PRODUCT AND METHODS OF FORMING SUCH A WELL TAP von Prabhu, Manjunatha, Ren, Hongru, Pritchard, David, Sporer, Ryan W

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Enlarged waveguide for photonic integrated circuit without impacting interconnect layers von Nummy, Karen A, Bian, Yusheng, Sporer, Ryan W

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