Multinode implementation of an extended Hodgkin–Huxley simulator von Chatzikonstantis, G., Sidiropoulos, H., Strydis, C., Negrello, M., Smaragdos, G., De Zeeuw, C.I., Soudris, D.J.

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A complete platform and toolset for system implementation on fine-grain reconfigurable hardware von Kalenteridis, V., Pournara, H., Siozos, K., Tatas, K., Vassiliadis, N., Pappas, I., Koutroumpezis, G., Nikolaidis, S., Siskos, S., Soudris, D.J., Thanailakis, A.

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Fine-grain reconfigurable platform: FPGA hardware design and software toolset development von Pappas, I, Kalenteridis, V, Vassiliadis, N, Pournara, H, Siozios, K, Koutroumpezis, G, Tatas, K, Nikolaidis, S, Siskos, S, Soudris, D J, Thanailakis, A

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A systematic methodology for mapping DSP algorithms onto multilevel array architectures von SOUDRIS, D. J., GEORGAKOPOULOS, P. D., GOUTIS, C.E.

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A VLSI design methodology for RNS full adder-based inner product architectures von Soudris, D.J., Paliouras, V., Stouraitis, T., Goutis, C.E.

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FPGA Architecture Design and Toolset for Logic Implementation von Tatas, K., Siozios, K., Vasiliadis, N., Soudris, D. J., Nikolaidis, S., Siskos, S., Thanailakis, A.

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A novel division algorithm for parallel and sequential processing von Tatas, K., Soudris, D.J., Siomos, D., Dasygenis, M., Thanailakis, A.

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Designing RNS and QRNS full adder based converters von Soudris, D.J., Dasigenis, M.M., Thanailakis, A.T.

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A CAD tool for architecture level exploration and automatic generation of RNS converters von Soudris, D.J., Dasigenis, M.M., Vasilopoulou, S.K., Thanailakis, A.T.

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A systematic methodology for designing multilevel systolic architectures von Soudris, D.J., Georgakopoulos, P.D., Goutis, C.E.

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Design methodology for systematic derivation of fault-tolerant array processors von Soudris, D.J., Poechmueller, P., Kyriakis-Bitzaros, E.D., Birbas, M.K., Goutis, C.E., Glesner, M.

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A method for detailed, short-term energy yield forecasting of photovoltaic installations von Anagnostos, D., Schmidt, T., Cavadias, S., Soudris, D., Poortmans, J., Catthoor, F.

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Design methodology of mapping iterative algorithms on piecewise regular processor arrays von Soudris, D.J., Birbas, M.K., Goutis, C.E.

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Systematic cross-validation of photovoltaic energy yield models for dynamic environmental conditions von Anagnostos, D., Goverde, H., Catthoor, F., Soudris, D., Poortmans, J.

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A method for detailed, short-term energy yield forecasting of photovoltaic installations von Anagnostos, D, Schmidt, T, Cavadias, S, Soudris, D, Poortmans, J, Catthoor, F

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Design and implementation of a DDS-based multi-carrier GMSK modulator von Kesoulis, M. J., Koukourlis, C. S., Lygouras, J. N., Soudris, D., Sahalos, J. N.

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A Novel FPGA Configuration Bitstream Generation Algorithm and Tool Development von Siozios, K., Koutroumpezis, G., Tatas, K., Soudris, D., Thanailakis, A.

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Mapping DSP Applications to a High-Performance Reconfigurable Coarse-Grain Data-Path von Galanis, M. D., Theodoridis, G., Tragoudas, S., Soudris, D., Goutis, C. E.

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Efficient system-level prototyping of power-aware dynamic memory managers for embedded systems von Atienza, David, Mamagkakis, Stylianos, Poletti, Francesco, Mendias, Jose M., Catthoor, Francky, Benini, Luca, Soudris, Dimitrios

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Dynamic memory management design methodology for reduced memory footprint in multimedia and wireless network applications von Atienza, D., Mamagkakis, S., Catthoor, F., Mendias, J.M., Soudris, D.

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