Rethinking Digital Design: Why Design Must Change von Shacham, O, Azizi, O, Wachs, M, Qadeer, Wajahat, Asgar, Zain, Kelley, Kyle, Stevenson, John P, Richardson, Stephen, Horowitz, Mark, Lee, Benjamin, Solomatnikov, Alex, Firoozshahian, Amin

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Comparative evaluation of memory models for chip multiprocessors von Leverich, Jacob, Arakida, Hideho, Solomatnikov, Alex, Firoozshahian, Amin, Horowitz, Mark, Kozyrakis, Christos

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Comparing memory systems for chip multiprocessors von Leverich, Jacob, Arakida, Hideho, Solomatnikov, Alex, Firoozshahian, Amin, Horowitz, Mark, Kozyrakis, Christos

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Secure control flow prediction von Solomatnikov, Alex, Asanovic, Krste

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SECURE CONTROL FLOW PREDICTION von ASANOVIC, Krste, SOLOMATNIKOV, Alex

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SECURE CONTROL FLOW PREDICTION von Solomatnikov, Alex, Asanovic, Krste

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Verification of chip multiprocessor memory systems using a relaxed scoreboard von Shacham, Ofer, Wachs, Megan, Solomatnikov, Alex, Firoozshahian, Amin, Richardson, Stephen, Horowitz, Mark

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Understanding sources of inefficiency in general-purpose chips von Hameed, Rehan, Qadeer, Wajahat, Wachs, Megan, Azizi, Omid, Solomatnikov, Alex, Lee, Benjamin C., Richardson, Stephen, Kozyrakis, Christos, Horowitz, Mark

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CONFIGURABLE INTERCONNECT ADDRESS REMAPPER WITH EVENT RECOGNITION von PARRY, David, ASANOVIC, Krste, SOLOMATNIKOV, Alex, SMITH, Joshua, BARBIER, Drew

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SECURE CONTROL FLOW PREDICTION von Loisel, Yann, Solomatnikov, Alex, Bresch, Cyril, Asanovic, Krste

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Using a configurable processor generator for computer architecture prototyping von Solomatnikov, Alex, Firoozshahian, Amin, Shacham, Ofer, Asgar, Zain, Wachs, Megan, Qadeer, Wajahat, Richardson, Stephen, Horowitz, Mark

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HICAMP: architectural support for efficient concurrency-safe shared structured data access von Cheriton, David, Firoozshahian, Amin, Solomatnikov, Alex, Stevenson, John P., Azizi, Omid

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HICAMP: architectural support for efficient concurrency-safe shared structured data access von Cheriton, David, Firoozshahian, Amin, Solomatnikov, Alex, Stevenson, John P., Azizi, Omid

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Chip multi-processor generator von Solomatnikov, Alex, Firoozshahian, Amin, Qadeer, Wajahat, Shacham, Ofer, Kelley, Kyle, Asgar, Zain, Wachs, Megan, Hameed, Rehan, Horowitz, Mark

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A memory system design framework: creating smart memories von Firoozshahian, Amin, Solomatnikov, Alex, Shacham, Ofer, Asgar, Zain, Richardson, Stephen, Kozyrakis, Christos, Horowitz, Mark

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Configurable interconnect address remapper with event recognition von BARBIEREW, PARRY, DAVID, SOLOMATNIKOV, ALEX, SMITH, JOSH, ASANOVIC, KRSTE

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Comparing memory systems for chip multiprocessors von Leverich, Jacob, Arakida, Hideho, Solomatnikov, Alex, Firoozshahian, Amin, Horowitz, Mark, Kozyrakis, Christos

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Understanding sources of ineffciency in general-purpose chips von Hameed, Rehan, Qadeer, Wajahat, Wachs, Megan, Azizi, Omid, Solomatnikov, Alex, Lee, Benjamin C., Richardson, Stephen, Kozyrakis, Christos, Horowitz, Mark

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Understanding Sources of Inefficiency in General-Purpose Chips von HAMEED, Rehan, QADEER, Wajahat, WACHS, Megan, AZIZI, Omid, SOLOMATNIKOV, Alex, LEE, Benjamin C, RICHARDSON, Stephen, KOZYRAKIS, Christos, HOROWITZ, Mark

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US generator for multi-processor chip cuts NRE costs but can still be customised and produce a small die von Flaherty, Nick

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